Sol–gel MgO thin films for insulation on SiC

Silicon carbide (SiC) is a wide bandgap semiconductor suitable for high-voltage, high-power, and high-temperature devices from DC to microwave frequencies. However, the marketing of advanced SiC power devices remains limited due to performance limitation of the SiO₂ dielectric among other issues. Indeed, SiO₂ has a dielectric constant 2.5 times lower than SiC, which means that at critical field for breakdown in SiC, the electric field in the adjoining SiO₂ becomes too high for reliable operation. This suppresses the main advantage of using SiC power devices if the ten times higher breakdown field for SiC in comparison to Si cannot be exploited. Therefore, alternative dielectrics having a dielectric constant higher or in the same order as SiC (ε_r≈10) should be used to reduce the electrical field in the insulator. Among alternative dielectrics to silicon dioxide (SiO₂), magnesium oxide (MgO) seems to be a good candidate regarding its bulk properties: large bandgap, high thermal conductivity and stability, and a suitable dielectric constant (ε_r≈10). In order to evaluate such a promising candidate, the sol–gel process appears to be a convenient route to elaborate this kind of coatings. By selecting an appropriate precursor solution and optimizing the curing conditions of the films, MgO films could be obtained under various crystallization states: non-oriented or preferred [1 1 1] orientation. MIM structures have been used to investigate the insulating properties of the sol–gel MgO films. The dielectric strength of the films was found to be microstructure–dependent, and reached 3 to 8 MV/cm at room temperature. Leakage currents were measured from 150 up to 250 °C, with values less than 10⁻⁵ A/cm² at 1 MV/cm.     

Influence of pinning trap in Ti/4H–SiC Schottky barrier diode

Ti/4H–SiC Schottky barrier diode without any intentional edge termination is fabricated. The obtained properties, low on-resistance of 3 mΩ cm² and low leakage current of 10⁻⁴ A/cm² at 1000 V, are evaluated by device simulation considering pinning at metal/semiconductor interface. The breakdown voltage is explained by minimization of electric field enhancement at the Schottky electrode edge due to pinning. The leakage current corresponds to Schottky barrier tunneling current depending on drift layer doping and Schottky barrier height.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

Design of field-plate terminated 4H-SiC Schottky diodes using high-k dielectrics

Silicon carbide (SiC) field-plate terminated Schottky diodes using silicon dioxide (SiO₂) dielectric experience high electric field in the insulator and premature dielectric breakdown, attributed to the lower dielectric constant of the oxide. To alleviate this problem we explore the use of high-k dielectrics, silicon nitride (Si₃N₄) and sapphire (Al₂O₃), on 4H-SiC by numerical simulations using Medici. The simulation results show significant improvement in blocking voltages by as much as 30% and much lower electric field within the dielectrics. There is also a slight reduction in the specific-on resistance (R_sp-on) and a small increase in the forward current density due to the formation of an accumulation layer in SiC where the metal overlaps the dielectric. This effect is enhanced with increasing dielectric constant and decreasing dielectric thickness for a given dielectric.     

Modeling the effect of thin gate insulators (SiO2, SiN,Al2O3 and HfO2) on AlGaN/GaN HEMT forward characteristics grown on Si,sapphire and SiC

GaN-based high electron mobility transistors (HEMTs) with a Schottky metal gate have been demonstrated to be an excellent candidate for high frequency, high temperature and high power applications. Nevertheless, their typical (and virtually inevitable) high gate leakage current, severely limits gate voltage swing, output power and breakdown voltage. GaN metal–insulator –semiconductor HEMTs or MIS-HEMTs (formed by introducing a thin dielectric film between the gate metal and semiconductor) is one of the effective solutions that reduce gate leakage and improve device performance. In this work, we evaluate the effect that the introduction of this gate insulator has on the on-state of the HEMT. For this reason, we develop a complete set of compact closed-form expressions for the evaluation of on-resistance, drain and saturation current and transconductance for a MIS-HEMT. This physical-based model describes the mobility in a 2D electron gas channel by means of optical phonon scattering and is explored with insulators based on SiO₂, SiN_x, Al₂O₃, and HfO₂.     

Advances in SiC power MOSFET technology

In recent years, SiC has received increased attention because of its potential for a wide variety of high temperature, high power, high frequency, and/or radiation hardened applications under which conventional semiconductors cannot adequately perform. For semiconductor devices designed to operate in these harsh conditions, SiC offers an unmatched combination of electronic and physical properties. The availability of SiC wafers on a commercial basis has led to the demonstration of many types of metal-oxide semiconductor (MOS)-gated devices that exploit its unique properties. To which extent the potential of SiC power MOSFET can be utilized is a question of appropriate SiC polytype, device structure, MOS interface quality and maturity of the technology. This paper reviews the present status of the SiC power MOSFETs technology that is approaching commercialization. Emphasis is placed upon the impact of SiO₂–SiC interface quality on the performance of SiC MOSFETs.     

Report on 4H–SiC JTE Schottky diodes

4H–SiC Schottky diodes with and without Junction Terminate Extension (JTE) have been fabricated using Ni for contact and boron for p+ implant. Electrical characterization showed a rectifying behaviour in the on-state. In the reverse mode, the un-terminated Schottky diode demonstrated a breakdown voltage of approximately 200 V, while the JTE structure exhibited a significant improved breakdown performance, and the blocking voltage over 450 V. Optical microscope examination revealed the surface flashover failure located at the metal contact periphery for the un-terminated Schottky diode, while the JTE structure failed in the central area of the metal contact. Both the experimental and theoretical analyses confirmed the JTE structure enhancement on the reliability for SiC Schottky diode performance in reverse mode.     

Optimized design of 4H-SiC floating junction power Schottky barrier diodes

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics.Compared with the conventional power Schottky barrier diode,the device structure is featured by a highly doped drift region and embedded floating junction region,which can ensure high breakdown voltage while keeping lower specific on-state resistance,solved the contradiction between forward voltage drop and breakdown voltage.The simulation results show that with optimized structure parameter,the breakdown voltage Can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide,High‐k,and Layered Dielectrics

Thin dielectric films are essential components of most micro‐ and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO₂, HfO₂, and Al₂O₃), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new‐concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.     

4H-SiC双层浮结肖特基势垒二极管温度特性研究

为了增强器件高温条件下的适应性,对4H-SiC双层浮结肖特基势垒功率二极管的温度特性进行了研究.结果表明,当温度变化时,器件的阻断电压、通态电阻、反向漏电流及开关时间等电学性质均要发生一定的变化.作为一种基于浮结技术的sic新器件,通过数值模拟方法对其特征参数进行优化,可使其承载电流能力、阻断特性和开关速度等得到进一步...     

Initial leakage current related to extrinsic breakdown in HfO2/Al2O3 nanolaminate ALD dielectrics

Multiple successive breakdown events are reported for HfO₂/Al₂O₃ nanolaminate dielectrics grown by atomic-layer deposition. The first breakdown distribution is not a Weibull distribution and shows a long TBD tail at high failure percentiles. Analysis of the correlation between time-to-breakdown and initial current leakage allows identifying this tail with extrinsic breakdown. Screening of the data to eliminate the extrinsic tail demonstrates that the successive breakdown events are completely uncorrelated and perfectly match the successive breakdown theory. The statistical correlation between initial current and extrinsic breakdown distribution is explained in terms of variations of the unintentional interfacial SiO_x layer at the silicon substrate/dielectric interface.     

Theoretical Investigation of Dielectric Materials for Two‐Dimensional Field‐Effect Transistors

Two‐dimensional dielectric materials that can inhibit electronic leakage are vital for developing next‐generation all‐2D electronic devices. However, few comprehensive studies of the atomistic nature of 2D insulating dielectrics currently exist. In this work, computational design strategies based on density functional theory and quantum dynamics simulations are used to assess the charge permeability through dielectric materials. Promising 2D dielectrics are considered, including monolayer SiC, hBN, and BeO, which possess promising properties and a honeycomb structure compatible with that of MoS₂, currently the most commonly used channel material in all‐2D transistors. A useful protocol for discovering promising dielectrics is described. The atomic structures of the interfaces are determined and their stabilities are evaluated by studying the interface formation energies and the presence of stress/strain at the interfaces. The interface electronic structures are characterized by studying the band structures, band offsets, and charge transfer at the interface. These important quantities reveal that all three materials chosen are good dielectric materials, but SiC is the poorest among them, BeO has the best insulting properties as a monolayer and hBN prevents the most charge leakage at the interface. It is shown how this protocol can also consider the effects of external potentials and temperatures.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Gate insulators and interface effects in organic thin-film transistors

This paper presents a detailed characterization of different thermosetting polymers to be used as gate dielectrics in organic thin-film transistors. Selected materials yield smooth films with good insulation properties and offer attractive processing conditions. Bottom-gate transistors were prepared using these dielectrics and compared to hybrid transistors with surface-treated SiO₂ as the dielectric. Gate bias induced leakage and solvent effects were investigated by preparing metal/insulator/semiconductor devices. Poly(3-hexylthiophene) (P3HT) transistors with organic dielectrics exhibited higher channel conductivity and lower mobility values with respect to P3HT-hybrid transistors and pentacene transistors. The importance of dielectric/semiconductor interface was discussed by comparing the performances of pentacene and P3HT transistors produced on different dielectrics.     

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45?nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I _on/I _off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO₂ (zirconium-di-oxide) is found out to be the best alternative for SiO₂ (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.     

Reliability of gate dielectrics and metal–insulator–metal capacitors

In this review paper reliability characterisation methods of SiO₂ as gate dielectric and metal–insulator–metal capacitors with various dielectrics are discussed. It includes the test structure design, the stress and measurement sequences, the raw data analysis and the extrapolation models of measured time to breakdown to lifetimes at operating conditions and targeted product failure rates. For each topic various references are given where further details are described. Especially pitfalls of approaches and problem areas are highlighted.     

A new 4H-SiC lateral merged double Schottky (LMDS) rectifier withexcellent forward and reverse characteristics

The novel characteristics of a new Schottky rectifier structure, known as the lateral merged double Schottky (LMDS) rectifier, on 4H-SiC are explored theoretically and compared with those of the compatible conventional 4H-SiC Schottky rectifiers. The anode of the proposed lateral device utilizes the trenches filled with a high barrier Schottky (HBS) metal to pinch off a low barrier Schottky (LBS) contact during reverse bids. Numerical simulation of any such SiC structure is complicated by the fact that the thermionic emission theory predicts the reverse leakage current to be orders of magnitude smaller than the measured data. We, therefore, first propose a simple empirical model for barrier height lowering to accurately estimate the reverse leakage current in a SiC Schottky contact. The accuracy of the empirical model is verified by comparing the simulated reverse leakage current with the reported experimental results on different SiC Schottky structures. Using the proposed empirical model, the two-dimensional (2-D) numerical simulations reveal that the new LMDS rectifier demonstrates about three orders of magnitude reduction in the reverse leakage current and two times higher reverse breakdown voltage when compared to the conventional lateral low barrier Schottky (LLBS) rectifier while keeping the forward voltage drop comparable to that of the conventional LLBS rectifier