Scheduling algorithms for shared fiber-delay-line optical packet Switches-part II: the three-stage clos-network case

In all-optical packet switching, packets may arrive at an optical switch in an uncoordinated fashion. To prevent packet loss in the switch, fiber delay lines (FDLs) are used as optical buffers to store optical packets. However, assigning FDLs to the arrival packets to achieve high throughput, low delay, and low loss rate is not a trivial task. In the authors' companion paper, several efficient scheduling algorithms were proposed for single-stage shared-FDL optical packet switches (OPSs). To further enhance the switch's scalability, this work was extended to a multistage case. In this paper, two scheduling algorithms are proposed: 1) sequential FDL assignment and 2) multicell FDL assignment algorithms for a three-stage optical Clos-Network switch (OCNS). The paper shows by simulation that a three-stage OCNS with these FDL assignment algorithms can achieve satisfactory performance.     

Optical contention resolution and buffering module for ATM networks

A new type of buffering module is introduced, suitable for incorporation into optical switch fabrics handling ATM cells. It comprises 2*2 optical switches and optical delay lines, and is equivalent to two interlinked buffers. Performance is characterised in terms of attenuation, crosstalk and cell loss.<>     

Optical input buffers for the HiPower photonic ATM switch-analysisand experiments

We describe an optical input buffer for the HiPower photonic ATM switch. This buffer can control the cell throughput in accordance with back pressure signals and incoming optical cells. We analyze the cell loss probability of the optical input buffer. Only a small buffer size of five is needed to obtain a cell loss probability of less than 10^-15 with 1024 ports. Experimental 10 Gb/s operation using optical fiber delay lines with gate control circuits shows that the bit error rate of the buffer is less than 10^-12     

Dimensioning of the Wavelength Converters in a WDM Optical Packet Switch

This paper analyzes the performances of a WDM optical packet switch making use of fiber delay lines to resolve output packet contentions; the optical packet switch is equipped with tunable wavelength converters which can shift optical packets to any wavelength of the output link which they are directed to. As not all packets need conversion, we propose a dimensioning technique allowing to reduce the number of converters and to improve the signal quality by reducing unnecessary conversions. The obtained results show that a remarkable reduction of the number of converters is obtained with respect to that needed by other switches described in literature. Such a saving is achieved by maintaining the packet loss probability below a prefixed threshold.     

Scheduling scheme using Look-ahead Buffer and Loop-back Buffer in Two-stage variable optical packet switch

Programmable variable delay lines have been developed, so as to delay packets in variable durations by combining several lengths of Fiber Delay Lines (FDLs) in optical packet switch. In practice, Two-stage variable optical packet switch with this programmable variable delay lines has been proposed. This switch has two buffers. The one is the programmable variable delay lines (Look-ahead Buffer). The other is the fixed FDLs that re-input a packet from the output to the input (Loop-back Buffer). The switch can foresee following packets and avoid contentions effectively by using two buffers. However, existing studies only focus on the Look-ahead Buffer. Intelligent usage of the Loop-back Buffer is actually out of concern. This paper proposes a sophisticated scheduling method in the Two-stage switch. The proposed method controls both the Look-ahead Buffer and the Loop-back Buffer cooperatively and improves the utilization of the switching process. The proposed method uses the Loop-back Buffer adaptively and distributes traffics in time and space domain. The effectiveness of the proposed method is evaluated through extended simulation experiments and basic hardware design.     

SLOB: a switch with large optical buffers for packet switching

Recently, optical packet switch architectures, composed of devices such as optical switches, fiber delay lines, and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future large electronic switch cores. However, attaining the buffer size (buffer depth) in optical packet switches required in practice is a major problem; in this paper, a new solution is presented. An architectural concept is discussed and justified mathematically that relies on cascading many small switches to form a bigger switch with a larger buffer depth. The number of cascaded switches is proportional to the logarithm of the buffer depth, providing an economical and feasible hardware solution. Packet loss performance, control and buffer dimensioning are considered. The optical performance is also modeled, demonstrating the feasibility of buffer depths of several thousand, as required for bursty traffic     

Contention resolution and QoS provisioning using sparse fiber delay lines in WDM networks

In this paper, we combine fiber delay lines (FDL) and optical wavelength conversion (OWC) as the solution for the burst contention problem in optical burst switching (OBS). We present a placement algorithm, k-WDS, for the sparse placement of FDLs at a set of selected nodes in the network. The algorithm can handle both uniform and non-uniform traffic patterns. Our extensive performance tests show that k-WDS provides more efficient placement of optical fiber delay lines than the well-known approach of placing the resources at nodes with the highest experienced burst loss. Performance results are also given to compare the benefit of using FDLs alone, OWCs alone, as well as a mixture of both FDLs and OWCs. A new algorithm, A-WDS, for the placement of an arbitrary numbers of FDLs and OWCs is presented and evaluated under different uniform and non-uniform traffic loads using network simulation of the NSFNET topology and randomly generated graphs. The paper is concluded by presenting the design of a cost-effective optical switch equipped with variable-delay FDL bank. Based on the switch design, a scheme to provide differentiated services for multiple classes of traffic is presented and evaluated.     

A Surjective-Mapping Based Model for Optical Shared-Buffer Cross-Connect

A Surjective-Mapping based Model (SMM) is developed to evaluate the performance of a slotted optical shared-buffer cross-connect. The model is simple, accurate, and yet provides comprehensive performance characteristics of the switch. The model also overcomes the limitations of traditional Markovian based models in evaluating moderate to large switches, associated with the explosion of number of states. The model is verified using simulation results for different switch sizes and different numbers of delay lines. The model enables dimensioning the switch architecture to meet the target performance. Performance of optical shared-buffer cross-connect is analyzed in detail, in terms of blocking probability, delay distribution, and delay line utilization     

An optical switch architecture for Manhattan networks

An electronically controlled optical packet deflection switch that is based on space and time switching at intermediate nodes is described. The switch uses optical delay lines to store and switch packets in the optical domain so that optical bandwidth can be achieved across the network. The optical switch is controlled by an associated electronic mechanism that provides the necessary versatility and processing power. This approach combines the advantages of the optics and the electronics. The use and performance of the switch are demonstrated in the context of the Manhattan deflection network     

Approximate Modeling of Optical Buffers for Variable Length Packets

This paper addresses the problem of dimensioning buffers realized by means of fiber delay lines in optical routers able to switch packets that have variable length and are sent asynchronously on the optical links. The optical buffer is analyzed focusing on the different behavior of a delay buffer and an electronic memory. The role of the time unit of the fiber delay lines is discussed, showing that it is a crucial parameter to determine the queuing performance. The paper presents two approximate analytical models that can be used both for analysis and engineering of the optical buffer and in particular to dimension the buffer time unit in an way that is optimal with respect to packet loss probability. The first model is based on an infinite queuing approximation. It is not very accurate and is valid for a limited set of values of the traffic load, but is extremely simple. The second model is based on a finite queuing approximation. It is more complex but more accurate and is valid for any value of traffic load. The accuracy of the models is compared with simulation and their range of applicability purposes is discussed.     

Compact polarization-insensitive InGaAsP-InP 2 /spl times/ 2 optical switch

We demonstrate a simple, compact, high-contrast ratio, and low-loss polarization-insensitive InGaAsP-InP 2 /spl times/ 2 optical switch with an operational wavelength range from 1520 to 1580 nm. The switch is 1.3 mm long by 160 /spl mu/m wide. The on-off contrast ratio is within (21/spl plusmn/2) dB over the temperature range from 16/spl deg/C to 64/spl deg/C, the polarization sensitivity is <2 dB, and the propagation loss is (3/spl plusmn/2) dB in both the ON and OFF states, making it potentially useful for optical cross-connects, delay lines, and add-drop multiplexers.     

Scheduling algorithms for shared fiber-delay-line optical packet Switches-part I: the single-stage case

In all-optical packet switching, packets may arrive at an optical switch in an uncoordinated fashion. When contention occurs, fiber delay lines (FDLs) are needed to delay (buffer) the packets that have lost the contention to some future time slots for the desired output ports. There have been several optical-buffered switch architectures and FDL assignment algorithms proposed in the literature. However, most of them either have high implementation complexity or fail to schedule in advance departure time for the delayed packets. This paper studies the packet scheduling algorithms for the single-stage shared-FDL optical packet switch. Three new FDL assignment algorithms are proposed, namely sequential FDL assignment (SEFA), multicell FDL assignment (MUFA), and parallel iterative FDL assignment (PIFA) algorithms for the switch. The proposed algorithms can make FDLs and output-port reservation so as to schedule departure time for packets. Owing to FDL and/or output-port conflicts, the packets that fail to be scheduled are discarded before entering the switch so that they do not occupy any FDL resources. It is shown by simulation that with these algorithms, the optical-buffered switch can achieve a loss rate of /spl sim/10/sup -7/ even at the load of 0.9. These algorithms are extended to the three-stage Clos-Network optical packet switches in the companion paper.     

Optical drive requirements for laser-activated semiconductor switches

Laser-activated semiconductor switch (LASS) devices of the thyristor type exhibit three regimes of operation. At low optical drive, optical triggering is obtained with delay time before conduction and relatively low current rise rates. At intermediate drive levels, fast switching is obtained with no appreciable delay time and fast current rise rates (greater than 10⁹A/s) but with substantial power lost in the switch element. At higher optical drives, saturated switching is observed with the rise rate and power loss relatively independent of the optical drive level. LASS thyristors of 1- and 4-kV operating voltage ratings have been characterized in the lossy fast switching regime. For pulses of 100-ns duration, the devices act as resistive elements. The magnitude of the resistance varies inversely with the optical drive, and can be understood as conductivity modulation of the conduction path by the photogenerated carriers. Such characterization allows switch system design tradeoff between the required optical drive level and the tolerable power loss in the switch elements.     

A prototype broadcast-and-select photonic ATM switch with a WDMoutput buffer

A rack-mounted prototype of a broadcast-and-select (B and S) photonic ATM switch is fabricated. This switch has an optical output buffer utilizing wavelength division multiplexed (WDM) signals. The WDM technology solves. The cell-collision problem in a broadcast-and-select network and leads to a simple network architecture and the broadcast/multicast function. The prototype can handle 10-Gb/s nonreturn-to-zero (NRZ) coded cells and 5-Gb/s Manchester-coded cells and has a switch size of four. In this prototype, the level and timing design are key issues. Cell-by-cell level fluctuation is overcome by minimizing the loss difference between the optical paths and adopting a differential receiver capable of auto-thresholding. The temperature control of delay lines was successful in maintaining the phase synchronization. Using these techniques, we are able to provide a WDM highway with a bit error rate of less than 10^-12. Fundamental photonic ATM switching functions, such as optical buffering and fast wavelength-channel selection, are achieved. We show our experimental results and demonstrate the high performance and stable operation of a photonic ATM switch for use in high-speed optical switching systems as an interconnect switch for a modular ATM switch and an ATM cross-connect switch     

光学延时物理机质及最新进展研究

分析了光学延时相控阵雷达（天线）国内外研究现状、研究机构及最新研究进展,提炼出普通和色散光纤延时线、波分复用技术结合多波长激光器光学延时、自由空间段结合液晶开关光学延时、布拉格、啁啾光纤光栅光学延时、平面波导技术光学延时、声光技术光学延时的相控阵分类及关键技术和代表性图示,评述了光学延时相控阵雷达（天线）国内外研究概貌。     

X波段可编程光钎传输微波延迟系统

介绍了X波段可编程光纤传输微波延迟系统的基本工作原理及系统组成。叙述了该系统的研制过程,包括:光发射模块、光接收模块和光纤延迟链路的设计。微波延迟系统具有低插入损耗、低延迟相关损耗,输出幅度稳定,快速延迟切换速度(<0.5 ms)等优点以及单板机编程和计算机控制界面。该延迟系统传输微波频率范围:9~11 GHz,延迟时间范围为1.013 3~1.646 7μs,延迟精度为0.5 ns,延迟时间可以在1.013 3~1.646 7μs范围内步进调节,延迟时间控制实现了计算机控制。     

Heuristic performance model of optical buffers for variable length packets

Optical switching (optical packet switching, optical burst switching, and others) provides alternatives to the current switching in backbone networks. To switch optically, also packet buffering is to be done optically, by means of fiber delay lines (FDLs). Characteristic of the resulting optical buffer is the quantization of possible delays: Only delays equal to the length of one of the FDLs can be realized. An important design challenge is the optimization of the delay line lengths for minimal packet loss. To this end, we propose a heuristic based on two existing queueing models: one with quantization and one with impatience. Combined, these models yield an accurate performance modeling heuristic. A key advantage of this heuristic is that it translates the optical buffer problem into two well-known queueing problems, with accurate performance expressions available in the literature. This paper presents the heuristic in detail, together with several figures, comparing the heuristic’s output to existing approaches, validating its high accuracy.     

Multibuffer delay line architectures for efficient contentionresolution in optical switching nodes

This paper proposes an efficient contention resolution switching architecture which can serve as the basis for all-optical switching nodes. The presented solution builds on fiber delay lines used as temporary optical storage and 2×2 space photonic switches, a solution principle also known as Quadro or switched delay lines (SDLs). The efficiency of SDLs is fundamentally linked to its storage capacity, i.e., the length of the fiber delay lines, while its cost depends on the number of 2×2 photonic switches, i.e., the number of stages in the switch. This work presents a solution that makes use of multibuffer fiber delay lines which allow multiple packets to be concurrently stored (propagated) on each line. With a novel switch control, it is shown that this solution increases the total storage capacity and significantly improves switch and network performance, without increasing the number of the 2×2 switches in the system, i.e., its cost     

基于SP4T开关的4位MEMS开关线式移相器设计

设计了一款4位MEMS开关线式移相器,由SP4TMEMS开关和微带传输线构成,工作于X波段。单刀四掷(single pole 4throw,SP4T)开关用于切换两条不同电长度的信号通道,即参考相位通道和延迟相位通道。每个SP4T开关包含4个悬臂梁接触式RF MEMS串联开关。介绍了4位MEMS开关线式移相器的总体设计,并给出了其关键部件SP4T开关和相位延迟线的设计细节。采用ADS软件仿真分析了器件的电气性能。仿真分析得到:SP4T开关在中心频率10GHz处的回波损耗为-36dB,插入损耗约为0.18dB;移相器各相位的回波损耗均低于-15dB,插入损耗为-0.8～-0.4dB。这种射频MEMS移相器具有小型化、低功耗和高隔离度的优点。     

A 32-element 8-bit photonic true-time-delay system based on a 288 /spl times/ 288 3-D MEMS optical switch

A large-scale three-dimensional microelectromechanical-system optical switch is used for the first time to realize a true-time-delay (TTD) beamformer for phased-array radar applications, with a capacity of 32 antenna elements and eight bits of delay. The 288 /spl times/ 288 optical switch has a median loss of 1.4 dB and all measured 82 944 paths exhibit less than 2.3 dB loss at 1310 nm. The TTD beamformer exhibits a loss variation of 1.5 dB, which is equalized using a mirror-offset technique.