在退火过程中离子注入杂质再分布的二维精确解析模型

<正> 一、引言 离子注入是大规模集成电路制造中的重要工艺,离子注入及其热退火过程中杂质再分布的模拟,对集成电路的设计和制造有很大指导意义。随着集成电路工艺的不断发展,器件尺寸越来越小,已出现了亚微米器件。因此,一维模型已不能很好描述热退火后离子注入杂质的分布,国外已大量应用二维、三维模型来描述。本文在二维离子注入模拟器FUTIS描述的注入杂质分布基础上,导出了在热退火过程中注入杂质再分布的二维解析解。     

用二维数值计算得到三维p-n结击穿特性的方法

本文基于大多数p-n结的结面形状在平行于表面的横剖面上常表现为一由光刻图形的圆角决定的圆弧这一特点,提出了一种把三维计算简化为二维计算的数值计算方法.用此方法对平面p-n结的击穿特性进行了分析,得到了平面p-n结击穿电压随图形圆角的曲率而变的曲线.本方法还可推广应用于对圆角区其他特性的研究.     

共漏极双功率MOSFET封装研究

针对适用于锂电池保护电路特点要求的共漏极功率MOSFET的封装结构进行了研发和展望.从传统的TSSOP-8发展到替代改进型SOT-26,一直到芯片级尺寸的微型封装外形,其封装效率越来越高,接近100%.同时,在微互连和封装结构的改进方面,逐渐向短引线或焊球无引线、平坦式引脚、超薄型封装和漏极焊盘散热片暴露的方向发展,增...     

纳米CMOS器件中源/漏串联电阻栅长相关性研究

本文利用恒定迁移率、直接I_d-V_gs和Y函数三种方法对纳米CMOS器件中提取的源/漏串联电阻(R_sd)与器件栅长(L)相关性进行了研究。结果表明,采用恒迁移率方法得到的R_sd具有与栅长无关的特性,纳米小尺寸CMOS器件的R_sd值在14.3Ω～10.9Ω之间。直接I_d-V_gs和Y函数方法都得到了与L相关的R_sd值,误差分析发现从直接I_d-V_gs和Y函数两种方法中提取的R_sd对L依赖性与提取过程中的栅极电压导致有效沟道迁移率(μ_eff)降低有关,推导过程中忽略了这种影响,R_sd值叠加了一个与栅长相关的量。本文计算了这个叠加的误差值,并得到消除此误差值之后各个栅长器件的R_sd值。     

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.     

从多子角度阐述p-n结理论

传统方法在分析p-n结理论时仅仅关注了过剩少子的扩散电流,但是随着其浓度梯度的降低,扩散电流趋于零,则电流的连续性将难以理解。另外,如果仅仅考虑过剩少子的注入,则无法理解"中性区"的电中性(即电中性条件将被破坏)。针对以上矛盾,以基本的器件物理为基础,分析并得到过剩多子必然存在于中性区,且其分布和数量与过剩少子相同,因而过剩多子的扩散电流也参与p-n结的电流输运。在充分考虑过剩多子的基础上,对p-n结的工作机理可以有更好、更深刻的理解。理想二极管方程在一些假设下仅仅考虑了空间电荷区两边过剩少子的扩散电流,提供了一个很巧妙地计算总电流的方法。     

Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel

Nanoscale double-gate (DG) FinFETs with undoped fin bodies are shown to have threshold voltages (Vt) that can be adjusted for independent I _ON and I _OFF control by allowing limited source/drain (S/D) dopants in the channel. S/D engineering of the lateral doping profile in the extension is proposed as a viable means for effecting such channel doping [as well as gate-S/D (G-S/D) underlap] and, thus, adjusting Vt for optimal I _ON/I _OFF in low-power and high-performance applications of nanoscale-FinFET CMOS. Physics-based device simulations, numerical simulations, and measured current-voltage characteristics are used to demonstrate and support the proposed Vt design approach.     

HgCdTe光伏器件反常I－V特性分析

对ＨｇＣｄＴｅ光伏器件研制中出现的光电二极管伏安特性反常现象提出了寄生ｐ－ｎ结模型，并以此模型为基点，结合工艺实验对此现象进行了解释和分析。     

A Quantum–Mechanical View on the Capacitance of a Silicon p-n Junction

We have calculated the capacitance of a silicon p-n junction from a self-consistent solution to the effective-mass Schroumldinger and Poisson equations. Although the p-n product and the charge distribution deviate strongly from the semiclassical calculations, the quantum mechanically calculated capacitance of the silicon p-n junction differs only weakly from the semiclassical result. We show that the deviation from the semiclassical result can be approximated as band-gap narrowing in the quasi-neutral regions due to the exchange-energy term in the effective-mass Schroumldinger equation     

A Study of PN Junction Diffusion Capacitance of MOSFET in Presence of Single Event Transient

In this paper, a 65 nm MOSFET 3D structure is built based on Technology Computer Aided Design (TCAD) 3D device simulation software, and the single-event transient (SET) effect in 65 nm CMOS inverter is analyzed using TCAD-HSPICE mixed-mode simulation based on heavy ion model. The formation and function of the PN junction diffusion capacitance in the Metal-Oxide-Semiconductor (MOS) device are discussed by analyzing the drain and substrate voltage characteristics of the device under the SET effect. Then the sub-circuit structure of this device for SET is established, and the mechanism of the diffusion capacitance of PN junction during the heavy ion action process is verified comparing with the results of sub-circuit HSPICE simulation results and the TCAD-HSPICE simulation results. Finally, A sub-circuit model is provided, to support circuit-level simulation of single-event effects.     

Quantitative Analysis of Dopant Distribution and Activation Across p-n Junctions in AlGaAs/GaAs Light-Emitting Diodes Using Off-Axis Electron Holography

Off-axis electron holography has been used to measure the electrostatic potential profile across the p-n junction of an AlGaAs/GaAs light-emitting diode with linearly graded triangular AlGaAs barriers. Simulations of the junction profile showed small discrepancies with experiment when the nominal dopant concentrations of Si and Be impurities were used. Revised simulations reproduced the measurements reasonably using reduced dopant levels that reflected the efficiency of dopant activation. Band-edge diagrams simulated with the nominal and revised dopant concentrations were also compared in terms of the effect that activation efficiency had on the AlGaAs barrier shape and carrier transport. It is concluded that electron holography measurements combined with modeling offer device designers and growers a helpful tool for analyzing and confirming doping profiles in complex heterostructures.      

Pulsed Laser Annealing of Silicon-Carbon Source/Drain in MuGFETs for Enhanced Dopant Activation and High Substitutional Carbon Concentration

We report for the first time, the use of pulsed laser annealing (PLA) on multiple-gate field-effect transistors (MuGFETs) with silicon-carbon (Si_1-xC_x) source and drain (S/D) for enhanced dopant activation and improved strain effects. Si_1-xC_x. S/D exposed to consecutive laser irradiations demonstrated superior dopant activation with a ~60% reduction in resistivity compared to rapid thermal annealed S/D. In addition, with the application of PLA on epitaxially grown Si_0.99C_0.01 substitutional carbon concentration C_sub increased from 1.0% (as grown) to 1.21%. This is also significantly higher than the C_sub of 0.71% for rapid thermal annealed Si_0.99C_0.01 S/D. With a higher strain and enhanced dopant activation, MuGFETs with laser annealed Si_0.99C_0.01 S/D show a ~53% drain-current improvement compared to MuGFETs with rapid thermal annealed Si_0.99C_0.01 S/D.     

Impacts of Dopant Segregation on the Performance and Interface-State Density of the MOSFET With FUSI NiSi Gate

MOSFET characteristics of NiSi fully silicidation of polysilicon gates are found to be influenced by preimplanted dopant. Dopant segregation induced by silicidation at gate/oxide interface is observed to affect threshold voltage, subthreshold swing, effective mobility, and interface characteristics. The degradation of MOSFET characteristics in B-doped NiSi metal gate is found to be related to increasing interface-state density due to silicidation-induced impurity segregation     

Breakdown voltage enhancement of the p-n junction by self-aligneddouble diffusion process through a tapered SiO2 implant mask

The low doping region extension at the edge of the junction curvature is implemented with the self-aligned double diffusion process using a tapered SiO₂ implant mask. The p⁺-p-n diodes fabricated with the proposed double diffusion process have relaxed the surface electric field at the junction curvature and increased the breakdown voltage by 140 V, compared with the cylindrical p-n junction. It is also found that the breakdown voltage of the p⁺ -p-n diodes having the field plate (FP) over the tapered oxide is 500 V, while that of the conventional p-n junction with the FP is 280 V     

A Comparative Study of Various MOSFET Models at Radio Frequencies

We have compared and systematically evaluated four mainstream MOSFET models (EKV, SPICE Level 3, Bsim3v3 and Philips MOS Model 9) at radio frequencies. Furthermore, we have tested some improvements proposed for the models in the GHz region. In the first phase complete scalable DC models were determined, and the high frequency model parameters were then extracted from properly designed RF test transistors by using S-parameter fitting and capacitance measurements. The inaccuracies in the AC results were found to be mainly a consequence of the problems in the modelling of the DC conductances. The Bsim3v3 and MOS9 models seem to yield the most realistic AC characteristics of the models. The accuracy of the MOS9 model is slightly inferior to that of the Bsim3v3 model, but it may be improved to the same level or even beyond, simply by adding a gate-bulk zero-bias capacitance to the MOSFET equivalent circuit, which has been done in many commercial circuit simulators. The best models give accurate results up to 4 GHz, and after a careful parameter extraction even at 10 GHz. We also have demonstrated the applicability of the improved models in the design of a LNA CMOS circuit.     

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

Sub-10-nm planar bulk CMOS devices were demonstrated by a lateral source/drain (S/D) junction control, which consists of the notched gate electrode, shallow S/D extensions, and steep halo in a reverse-order S/D formation. Furthermore, the transport properties were also evaluated by using those sub-10-nm planar bulk MOSFETs. The direct-tunneling currents between the S/D regions, with not only the gate length but also the “drain-induced tunneling modulation (DITM)” effects, are clearly observed for the sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical simulation reveals that the tunneling currents increase with the increase in the temperatures and gate voltages, resulting in a certain amount of contribution to the subthreshold current even at 300 K. Therefore, it is strongly required that the supply voltage should be reduced to suppress the DITM effects for the sub-10-nm CMOS devices even under the room-temperature operations.     

双掺硅片热氧化后形成p-n结的结深研究

本文着重研究双掺硅片热氧化后形成p-n结的结深规律.在理论上导出了p-n结的结深表达式:在一定的温度下,结深与氧化热处理时间的平方根成正比;并且与p型和n型杂质的掺杂比v有关,随着v增大,结深减小,实验结果与该式反映的规律基本吻合.     

The Effect of Nanoscale Nonuniformity of Oxygen Vacancy on Electrical and Reliability Characteristics of HfO2 MOSFET Devices

To understand the influence of oxygen vacancies in on the electrical and reliability characteristics, we have investigated area-dependent leakage-current characteristics of HfO₂ with large-area device and conducting atomic force microscopy (C-AFM). Unlike with the large-area analysis with typical capacitor and transistor, a clear evidence of oxygen vacancy was observed in nanoscale-area measurement using the C-AFM. Similar observations were made in various postdeposition annealing ambients to investigate the generation and reduction of oxygen vacancy in HfO₂ . With optimized postdeposition annealing for oxygen vacancy, significantly reduced charge trapping was observed in HfO₂ nMOSFET.     

N管开启电压调整注入对P－N结击穿电压的影响

为了讨论问题方便，定义了两种Ｐ－Ｎ结：“漏Ｐ－Ｎ结”和“单纯Ｐ－Ｎ结”。分析了二者击穿电压相关因素的差别，认为“漏Ｐ－Ｎ结”的击穿电压与沟道区杂质浓度密切相关。ＥＥＰＲＯＭ的研制中，要求“漏Ｐ－Ｎ结”击穿电压≥２０Ｖ，即沟道区杂质浓度要低到一定的程度，而同时又必须保证一定的开启电压，即沟道区杂质浓度要高到一定的程度。通过分析与实验，提出了解决这一矛盾的通用原则。