Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance

The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.     

MOSFET output characteristics after oxide breakdown

The performance of nMOSFETs after the gate oxide (SiO₂) dielectric breakdown (BD) has been studied. Different BD hardness, BD path locations along the channel and device aspect ratios have been considered. The results show that the BD of the gate oxide affects the overall I_D-V_DS characteristics and that the BD impact depends on BD hardness and location and device geometry. To describe the post-BD data, a simple BD MOSFET model has been used, which accounts for the after BD additional gate current and drain current effects. The model is able to fit all the observed post-BD behaviours and can be easily included in a circuit simulator, to evaluate the impact of device BD on the post-BD performance of circuits.     

Contributions of the gate current and channel current variation to the post-breakdown MOSFET performance

A new approach to the modelling of the post-breakdown (BD) performance of MOSFETs for circuit simulation is presented, which separately considers the additional post-BD gate current and the variation of the MOSFET channel current. The post-BD gate current is modelled using an improved equivalent circuit whereas the BSIM4 model is used to describe the MOSFET channel current. This approach has allowed to analyse the contributions of both currents on the post-BD I_D-V_D characteristics. The results show that the gate current increase and the variation of the channel current are determining factors of the MOSFET performance degradation after BD.     

A new approach to determine the effective channel length and thedrain-and-source series resistance of miniaturized MOSFET's

A new decoupled C-V method is proposed to determine the intrinsic (effective) channel region and extrinsic overlap region for miniaturized MOSFET's. In this approach, a unique channel-length-independent extrinsic overlap region is extracted at a critical gate bias, so bias-independent effective channel lengths (L_eff) are achieved. Furthermore, the two-dimensional (2D) charge sharing effect is separated from the effective channel region. Based on this L_eff and the associated bias-dependent channel mobility, μ_eff , the drain-and-source series resistance (R_DS) can be derived from the I-V characteristics for each device individually. For the first time, the assumption or approximation for R_DS and μ_eff can be avoided, thus the difficulties and controversy encountered in the conventional I-V method can be solved. The 2D charge sharing effect is incorporated into the bias-dependent R_DS. This bias dependence is closely related to the drain/source doping profile and the channel dopant concentration. The proposed L_eff and R_DS extraction method has been verified by an analytical I-V model which shows excellent agreements with the measured I-V characteristics     

Effect of oxide breakdown on RS latches

In this work, the influence of the oxide breakdown on RS latches performance has been analysed. The NAND and NOR RS latch topologies have been compared in terms of noise margin and switching times for different broken down transistors. Moreover, the influence of the additional current path due to BD and of the variation of the MOSFET parameters on the circuit functionality have been separately evaluated. The results show that RS latches do not lose functionality after BD. However, reductions on noise margin and variations on switching times are observed, which depend on the damaged transistor. The performance degradation of the circuit is mainly due to the additional post-BD gate current whereas the variation of the BD MOSFET parameters has only a small influence.     

Characterization of shallow silicided junctions for sub-quartermicron ULSI technology. Extraction of silicidation induced Schottkycontact area

The current-voltage (I-V) characteristics of shallow silicided p ⁺-n and n⁺-p junctions are presented. In the former the diode behavior was same as in nonsilicided junction, while drastic change in diode I-V was observed in the latter. The formation of Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n⁺-p junction in the forward bias region. Poole-Frenkel barrier lowering predominantly influenced the reverse leakage current, masking thereby the effect of Schottky contact. The leakage current in n⁺-p diodes was higher than in nonsilicided diodes by two orders of magnitude and this is consistent with the formation of Schottky contact via titanium or titanium-silicide penetrating into the p-substrate and generating trap sites. There is no increase in the leakage current and no formation of Schottky contact in case of the p⁺-n junction. The Schottky contact amounting to less than 0.01% of the total junction area and not amenable for SEM or TEM observation was extracted for the first time by simultaneous characterization of forward and reverse characteristics of silicided n ⁺-p diode     

Reverse short-channel effects on threshold voltage in submicrometersalicide devices

A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi₂ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices     

On Charge Transport and Low-Frequency Noise in the GaN p-i-n Diode

The current-voltage (I-V) characteristics and low-frequency noise of the GaN p-i-n diodes were investigated in temperature range from 10 K to 300 K. We found that the reverse biased p-i-n diode made of GaN/AlGaN exhibits features of the space charge limited (SCL) current flow and its I-V characteristics can be approximated by the power law I~Vⁿ relation. This phenomenon can be attributed to the presence of the multiple charge traps in the intrinsic region of device. It has been demonstrated that the direct tunneling from traps to bands may occur in diodes at forward and reverse bias with strong support of the Frenkel effect. The low frequency noise in our devices does not depend on temperature in both bias directions under cryogenic conditions. The observed low-frequency noise features support the hypothesis that excess tunneling current and recombination at grain boundaries are origins of the 1/f low-frequency noise in the diode at forward bias. The 1/f noise in the reverse bias regime can be described as a composition of many Lorentzian noise components that originate from traps, which have specific depth distribution     

Schottky-clamped NMOS transistors implemented in a conventional0.8-μm CMOS process

An 0.8-μm n-channel MOSFET with a TiSi₂-Si Schottky clamped drain-to-body junction (SCDR) and an n⁺ implanted standard source structure have been fabricated in a conventional 0.8-μm salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n⁺-drain/p-substrate/n⁺-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n⁺ drain-to-p-substrate guard-ring diode connected in parallel     

A new SPICE MOSFET Level 3-like model of HEMT's for circuitsimulation

A fully analytical model for the current-voltage (I-V) characteristics of HEMT's is presented. It uses a polynomial expression to model the dependence of sheet carrier concentration (n_s) in the two-dimensional electron gas (2-DEG) on gate voltage (V_G ). The resultant I-V relationship incorporates a correction factor α analogous to SPICE MOSFET Level 3 model and is therefore more accurate than models assuming a linear n_s-V_G dependence leading to square law type I-V characteristics. The model shows excellent agreement with experimental data over a wide range of bias. Further, unlike other models using nonlinear n_s-V_G dependence, it neither uses fitting parameters nor does it resort to iterative methods at any stage. It also includes the effects of the extrinsic source and drain resistances. Due to its simplicity and similarity in formulation to the SPICE MOSFET Level 3 model, it is ideally suited for circuit simulation purposes     

Reverse I-V characteristics in Au-GaAs Schottky diode in the presence of interfacial layer

The existence of an interfacial layer in an Au-GaAs Schottky diode may be revealed by measuring its I-V characteristics at very low reverse bias voltage. It is shown in this letter that a voltage dividing factor m can be used [see (2) of the text] to describe the effect of the interfacial layer on the I-V characteristics of the diode at low bias voltage.     

Substrate bias dependence of breakdown progression in ultrathin oxide pMOSFETs

Negative substrate bias-enhanced oxide breakdown (BD) progression in ultrathin oxide (1.4 nm) pMOS is observed. The enhanced progression is attributed to the increase of hole-stress current resulting from BD-induced, channel-carrier heating. The carrier temperature extracted from the spectral distribution of hot-carrier luminescence is around 1300 K. The substrate bias dependence of post-BD hole-tunneling current is confirmed from measurement and calculation. The observed phenomenon is particularly significant to ultrathin gate oxide reliability in floating substrate (SOI) and forward-biased substrate devices.     

Junction between amorphous germanium and monocrystal pSi

In the present investigation the electrical behaviour of SnO₂-ⁿ_pSi-aGe-Me (In, Al, Ag, and Cr) is presented. Almost ideal Schottky diode behaviour is exhibited in a narrow region of applied bias. The junction current at large external bias (V > 300 mV) is dominated by tunnelling and the associated barrier height of aGe on monocrystal Si agrees with values reported for metal-monocrystal Si. Presence of interface states becomes manifest from the I-V and C-V characteristics.     

Improving the reverse recovery of power mosfet integral diodes by electron irradiation

This paper demonstrates that controlled electron irradiation of silicon power MOSFET devices can be used significantly improve the reverse recovery characteristics of their integral reverse conducting diodes without adversely affecting the MOSFET characteristics. By using 3 MeV electron irradiation at room temperature it was found that the reverse recovery charge in the integral diode could be continuously reduced in a well controlled manner from over 500 nC to less than 100 nC without any significant increase in the forward voltage drop of the integral diode under typical operating peak currents. The reverse recovery time was also observed to decrease from 3 microseconds to less than 200 nsec when the radiation dose was increased from 0 to 16 Megarads. The damage produced in gate oxide of the MOSFET due to the electron radiation damage was found to cause an undersirable decrease in the gate threshold voltage. This resulted in excessive channel leakage current flow in the MOSFET at zero gate bias. It was found that this channel leakage current was substantially reduced by annealling the devices at 140°C without influencing the integral diode reverse recovery speed. Thus, the electron irradiation technique was found to be effective in controlling the integral diode reverse recovery characteristics without any degradation of the power MOSFET characteristics.     

Structure of the oxide damage under progressive breakdown

The I–V characteristics of ultra-thin gate oxides under progressive breakdown (BD) show a common behavior, indicative of well-defined general physical features of the BD spot. Transmission electron microscopy (TEM) observations give some hints about this structure and on this basis we propose a physical model of the post-BD current, which is in good agreement with data.     

SOI MOSFETI－V特性的计算机模拟

本文研究了ＳＯＩＭＯＳＦＥＴ的Ｉ－Ｖ特性，建立了一套模拟ＳＯＩ器件工作特性的解析模型，适用于不同的ＳＯＩ膜厚和各种前、背栅的偏置情况，在各种不同情况下由计算机自动选择适当模型进行拟合，该模型物理意义明确，计算简便快速，所用参数易于提取。     

Post-soft-breakdown characteristics of deep submicron NMOSFETs withultrathin gate oxide

The impacts of soft-breakdown (SBD) on the characteristics of deep sub-micron NMOSFETs were investigated. It is shown that the BD location plays a crucial role in the post-BD switching function of the device. When BD occurs at the channel, the turn-on behavior of the drain current would not be significantly affected, which is in strong contrast to the case of ED at the drain, Nevertheless, significant increase in gate current is observed in the off-state when the gate voltage is more negative than -1 V. Its origin is identified to be due to the action of two parasitic bipolar transistors formed after SBD occurrence at the channel     

Influence of oxide breakdown position and device aspect ratio on MOSFET’s output characteristics

In this work, the influence of oxide breakdown (BD) location on the MOSFET output characteristics has been studied taking into account the devices aspect ratio. The results show that the BD location plays an important role on the device output characteristics for any device geometry. The characteristics have been included on a circuit simulator in order to consider the BD influence on a three stage inverter. The simulation shows that the BD position can play an important role on circuit performance.     

Finite-element modeling of soft tissue rolling indentation

We describe a finite-element (FE) model for simulating wheel-rolling tissue deformations using a rolling FE model (RFEM). A wheeled probe performing rolling tissue indentation has proven to be a promising approach for compensating for the loss of haptic and tactile feedback experienced during robotic-assisted minimally invasive surgery (H. Liu, D. P. Noonan, B. J. Challacombe, P. Dasgupta, L. D. Seneviratne, and K. Althoefer, "Rolling mechanical imaging for tissue abnormality localization during minimally invasive surgery, " IEEE Trans. Biomed. Eng., vol. 57, no. 2, pp. 404-414, Feb. 2010; K. Sangpradit, H. Liu, L. Seneviratne, and K. Althoefer, "Tissue identification using inverse finite element analysis of rolling indentation," in Proc. IEEE Int. Conf. Robot. Autom. , Kobe, Japan, 2009, pp. 1250-1255; H. Liu, D. Noonan, K. Althoefer, and L. Seneviratne, "The rolling approach for soft tissue modeling and mechanical imaging during robot-assisted minimally invasive surgery," in Proc. IEEE Int. Conf. Robot. Autom., May 2008, pp. 845-850; H. Liu, P. Puangmali, D. Zbyszewski, O. Elhage, P. Dasgupta, J. S. Dai, L. Seneviratne, and K. Althoefer, "An indentation depth-force sensing wheeled probe for abnormality identification during minimally invasive surgery," Proc. Inst. Mech. Eng., H, vol. 224, no. 6, pp. 751-63, 2010; D. Noonan, H. Liu, Y. Zweiri, K. Althoefer, and L. Seneviratne, "A dual-function wheeled probe for tissue viscoelastic property identification during minimally invasive surgery," in Proc. IEEE Int. Conf. Robot. Autom. , 2008, pp. 2629-2634; H. Liu, J. Li, Q. I. Poon, L. D. Seneviratne, and K. Althoefer, "Miniaturized force indentation-depth sensor for tissue abnormality identification," IEEE Int. Conf. Robot. Autom., May 2010, pp. 3654-3659). A sound understanding of wheel-tissue rolling interaction dynamics will facilitate the evaluation of signals from rolling indentation. In this paper, we model the dynamic interactions between a wheeled probe and a soft tissue sample using the ABAQUS FE software package. The aim of this work is to more precisely locate abnormalities within soft tissue organs using RFEM and hence aid surgeons to improve diagnostic ability. The soft tissue is modeled as a nonlinear hyperelastic material with geometrical nonlinearity. The proposed RFEM was validated on a silicone phantom and a porcine kidney sample. The results show that the proposed method can predict the wheel-tissue interaction forces of rolling indentation with good accuracy and can also accurately identify the location and depth of simulated tumors.     

平面型RTD与BJT构成的串联单元特性分析

采用了n+-GaAs衬底和硼离子注入的新型工艺实现了共振隧穿二极管(RTD)的平面化,解决了台面型RTD工艺的不足,得到常温电流峰谷比为2.51∶的平面型RTD(PRTD);利用高级设计系统ADS电路模拟和实验测量对PRTD与BJT串联单元的不同串联方式的电压-电流特性进行了深入分析。这一特性的研究对RTD与异质结双极晶体管(HBT)、MOSFET、高电子迁移率晶体管(HEMT)等三端器件的结合具有普遍意义。