锑化铟离子注入退火技术研究

对锑化铟（InSb）铍离子（Be+）注入后的快速退火技术进行了研究,并对不同退火温度和时间的晶片进行了工艺实验,通过测试其PN结I-V特性,对比了不同快速退火条件对PN结特性的影响,确定在一定快速热退火条件下可以获得高质量的PN结,并对试验结果进行了分析。     

Lithographyless ion implantation technology for agile fab

A new type of ion implanter developed for an agile fab can eliminate the processes concerned. with photoresist lithography from the ion implantation process. This new ion implantation technology can reduce the raw process time, footprint, and the cost of ownership to less than one-half that of conventional ion implantation technology. The authors are making further developments on this ion implanter and evaluating technical issues related to ion implantation. This technique is suitable for manufacturing submicron node IC devices. Based on the results of evaluating the prototype machine, we will produce the next /spl beta/-machine.     

The influence of dose and protecting mask on electrically active defects induced by ion implantation in silicon

We present a study of electrically active defects induced by ion implantation, for two dopants: arsenic and phosphorous. Our analysis technique is Deep Level Transient Spectroscopy (D.L.T.S.). We have studied the generation of defects by direct implantation, and indirect implantation, that is through an SiO₂ layer. We follow the defect spectrum evolution for different doses (10⁸ to 10¹⁴ atoms/cm²) and for different annealing temperatures (from room temperature up to 800° C). The comparison of our results with other published ones allows us to improve the knowledge about the role of a protecting oxide layer, the influence of moderate thermal annealing, and the effect of oxygen on deep centers produced by ion bombardment.     

基于聚焦离子束注入的微纳加工技术研究

提出了聚焦离子束注入（focused ion beam implantation,FIBI）和聚焦离子束XeF2气体辅助刻蚀（gas assisted etching,GAE）相结合的微纳加工技术。通过扫描电镜观察FIBI横截面研究了聚焦离子束加工参数与离子注入深度的关系。当镓离子剂量大于1.4×1017ion/cm2时,聚焦离子束注入层中观察到均匀分布、直径10～15nm的纳米颗粒层。以此作为XeF2气体反应的掩膜,利用聚焦离子束XeF2气体辅助刻蚀（FIB-GAE）技术实现了多种微纳米级结构和器件加工,如纳米光栅、纳米电极和微正弦结构等。结果表明该方法灵活高效,很有发展前途。     

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

In order to fabricate strained-Si MOSFETs, we present a method to prepare strained-Si material with high-quality surface and ultra-thin SiGe virtual substrate. By sandwiching a low-temperature Si (LT-Si) layer between a Si buffer and a pseudomorphic Si0.08Ge0.2 layer, the surface roughness root mean square (RMS) is 1.02 nm and the defect density is 106 cm-2 owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si0.08Ge0.2 layer. By employing P+ implantation and rapid thermal annealing,the strain relaxation degree of the Si0.08Ge0.2 layer increases from 85.09% to 96.41% and relaxation is more uniform. Meanwhile, the RMS (1.1 nm) varies a little and the defect density varies little. According to the results, the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.     

低温硅结合离子注入技术制备应变Si材料

为制作应变硅MOS器件,给出了一种制备具有高表面质量和超薄SiGe虚拟衬底应变Si材料的方法。通过在Si缓冲层与赝晶Si0.8Ge0.2之间设置低温硅（LT-Si）层,由于失配位错限制在LT-Si层中且抑制线位错穿透到Si0.8Ge0.2层,使表面粗糙度均方根值（RMS）为1.02nm,缺陷密度系106cm-2。又经过P+注入和快速热退火,使Si0.8Ge0.2层的应变弛豫度从85.09%增加到96.41%,且弛豫更加均匀。同时,RMS（1.1nm）改变较小,缺陷密度基本没变。由实验结果可见,采用LT-Si层与离子注入相结合的方法,可以制备出满足高性能器件要求的具有高弛豫度、超薄SiGe虚拟衬底的高质量应变Si材料。     

Modeling ion implantation of HgCdTe

Ion implantation of boron is used to create n on p photodiodes in vacancy-doped mercury cadmium telluride (MC.T). The junction is formed by Hg interstitials from the implant damage region diffusing into the MC.T and annihilating Hg vacancies. The resultant doping profile is n⁺/n^-/p, where the n⁺ region is near the surface and roughly coincides with the implant damage, the n^- region is where Hg vacancies have been annihilated revealing a residual grown-in donor, and the p region remains doped by Hg vacancy double acceptors. We have recently developed a new process modeling tool for simulating junction formation in MC.T by ion implantation. The interstitial source in the damage region is represented by stored interstitials whose distribution depends on the implant dose. These interstitials are released into the bulk at a constant, user defined rate. Once released, they diffuse away from the damage region and annihilate any Hg vacancies they encounter. In this paper, we present results of simulations using this tool and show how it can be used to quantitatively analyze the effects of variations in processing conditions, including implant dose, annealing temperature, and doping background.     

Lateral ion implant straggle and mask proximity effect

Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.     

Effects and prevention of source/drain ion implantation into thepolysilicon in a BiCMOS technology

The implantation of source/drain dopants into the polysilicon for FET gates and the bipolar emitter has a profound effect on the operation of the devices. Although the collector current is only slightly affected, the base current increases by as much as a factor of three, with the emitter resistance doubled. The effect of altering the gate doping is evident in the FET devices as well. This paper describes the above device processes necessary to add a silicon nitride blocking layer     

A study of multi-energy ion implantation

A new calculation method of multi-energy ion implantation, i.e, “equivalent area method”, has been studied. An arbitrary density concentration or energy profile can be achieved, according to requirements of the device, by this method. It provides the basis of fabricating thin-film flat impurity profile devices. By use of this method, the Si-RAPD device with rectangular impurity profile, the Si-RAPD device with a particular low-high-low structure and the GaAs MESFET or IMPATT device with “horse head” type structure are designed and calculated. All results are satisfactary and the design of the new type device can be predicted by this method. The calculated results in this paper are well in agreement with the experimental values in literature.     

Strongly asymmetric doping profiles at mask edges in high-energyion implantation

The application of high-energy ion implantation is restricted by an asymmetric doping profile at the mask edges. As a result, buried interconnect cannot easily be formed. Moreover, the holding voltage and threshold voltage of CMOS-processes with retrograde wells may be strongly affected by this asymmetry. It arises from the 7° wafer tilt, which is frequently used to avoid channeling, even in the case of nearly perpendicular (82-85°) mask edges. On the mask side, which is incoming to the ion beam, a trunk to the surface has experimentally been observed. According to two-dimensional Gaussian and advanced Monte Carlo simulations, the doping concentration in this trunk is about 20% of the maximum concentration in the case of a 85° mask angle. The simulations predict the experimental results fairly well. The asymmetry effect of high energy ion implantations can also be visualized in photoresist by means of a damaged region     

x光纳米光刻掩模的离子束制备法

重离子束轰击聚碳酸酯后,对样品进行陈化和紫外线照射敏化,在优化条件下蚀刻后得到纳米孔径核孔膜。利用电化学沉积技术在核孔膜中制备了最小孔径为30纳米的铜纳米线。获得的铜纳米线/聚碳酸酯可以作为x光纳米光刻的掩模。     

亚半微米铬掩模版制作技术研究

介绍了用LeicaVB5电子束曝光系统在涂敷有PMMA电子束抗蚀剂的4英寸铬板上,通过扫描曝光、湿法显影、干法刻蚀等手段制作亚微米、亚半微米铬掩模版的工艺技术。     

Iron nitride mask and reactive ion etching of GaN films

One of the major GaN processing challenges is useful pattern transfer. Serious photoresist mask erosion and hardening are often observed in reactive ion etching of GaN. Fine pattern transfer to GaN films using photoresist masks and complete removal of remaining photoresist after etching are very difficult. By replacing the etch mask from conventional photoresist to a sputtered iron nitride (Fe-8% N) film, which is easily patterned by wet chemical etching and is very resistive to Cl based plasmas, GaN films can be finely patterned with vertical etched sidewalls. Successful pattern transfer is realized by reactive ion etching using Cl (H) containing plasmas. CHF₃/Ar, C₂ClF₅/Ar, C₂ClF₅/Ar/O₂, SiCl₄, and CHCl₃ plasmas were used to etch GaN. The GaN etch rate is dependent on the crystalline quality of GaN. Higher crystalline quality GaN films exhibit slower etch rates than GaN films with higher dislocation and stacking fault density.     

Monitoring of low-dose ion implantation in silicon

Monitoring of low-dose arsenic or boron ion implantation (doses: 5×10¹⁰ to 1×10¹³ cm^-2) in silicon, which is required for threshold voltage control of MOS transistors, is studied. The thermal-wave (TW) signal intensity decreases monotonically with decreasing dose. The lowest detection limit for As⁺ and B⁺ implantations is 5×10¹⁰ and 1×10¹¹ cm^-2, respectively. Correlation of the TW signal intensity versus damage density, TW intensity versus dose, and laser Raman intensity versus dose is obtained. The TW intensity is also correlated with the sheet conductance, and the threshold voltage of the transistor. Therefore, this technique is useful as a nondestructive, highly sensitive dose monitor for low-dose implantation to achieve tight threshold voltage control in MOS transistors     

数字掩模灰度细分技术研究

数字掩模技术是一种很有发展前途的衍射微光学元件制作技术。实际制作时,由于感光材料具有感光非线性,实际可利用的灰度数目将小于256。即使256级灰度全部可用,也无法实现曝光量的精细控制以达到一般的加工要求。文中提出了2种灰度细分的方法,即多SLM组合调制和彩色等效灰度技术。从理论上分析了2种方法均能实现灰度的细分,从而达到曝光量的精细控制。     

离子注入均匀性的工艺控制

叙述了影响离子注入均匀性的几个主要因素,其中包括束流品质,离子束聚焦与扫描以及束流大小选择等。同时介绍了如何控制这些因素来获取优异的注入均匀性,通过这些控制手段,均匀性可以优于１ ％ ,结果令人满意。     

Se+ ion implantation into encapsulated GaAs

PECVD Si3N4 was deposited on undoped SI (100) GaAs. Se+ ions were implanted with a dose of 1×1014 ions cm?2 at an ion energy of 400 keV through the Si3N4 layer. Annealing was carried out on a dual graphite strip heater at temperatures up to 900°C for 100 s. Transmission electron microscope studies show a large concentration of damage in the form of dense dislocation tangles and long-range strain centres at the Si3N4/GaAs interface. Below this sheet of gross damage the material contains a relatively low density of dislocation loops. Electrical measurements indicate that, for a similar implant condition directly into GaAs, a relatively high electrical activity is measured compared with that of the implants through the Si3N4 encapsulating layer.