不同集电结结构的AlGaInP/GaAs异质结双极晶体管

设计并制备了三种不同集电结结构的A lG aInP/G aA s异质结双极晶体管,计算给出了三种集电结能带结构。通过对三种HBT的直流特性测试表明,N pN型HBT因异质集电结的导带尖峰出现电子阻挡效应;N p iN型HBT集电结引入i-G aA s层能有效克服电子阻挡效应,同时还具有拐点电压Vknee小、开启电压Voffset小、击穿电压BVCEO大等优点,但由于i-G aA s层引入增加了基区电子扩散长度,使器件电流增益有所下降。     

电离总剂量效应对HfO2栅介质经时击穿特性影响

针对纳米金属-氧化物-半导体(MOS)器件中采用的高介电常数Hf栅介质,开展电离总剂量效应对栅介质经时击穿特性影响的研究。以HfO₂栅介质MOS电容为研究对象,进行不同栅极偏置条件下⁶⁰Co-γ射线的电离总剂量辐照试验,对比辐照前后MOS电容的电流-电压、电容-电压以及经时击穿特性的测试结果。结果显示,不同的辐照偏置条件下,MOS电容的损伤特性不同。正偏辐照下,低栅压下的栅电流显著增大,电容电压特性的斜率降低;零偏辐照下,正向高栅压时栅电流和电容均显著增大;负偏辐照下,栅电流均有增大,正向高栅压下电容增大,且电容斜率降低。3种偏置下,电容的经时击穿电压均显著减小。该研究为纳米MOS器件在辐射环境下的长期可靠性研究提供了参考。     

一种可集成高密度氮氧化硅介质工艺

针对传统二氧化硅、氮化硅等介质材料在制作MOS电容时存在电容密度低、界面特性差的问题,通过对氮离子注入、氮硅氧化实验的分析,成功开发出一种采用注入氮并氧化制作氮氧化硅介质材料的工艺;并使用该工艺研制出与36 V双极工艺兼容、介质的相对介电常数为5.51、击穿电压达81 V、电容密度为0.394 fF/μm²的高密度MOS电容,较传统可集成二氧化硅/氮化硅复合介质电容的电容密度提高了35.86%。该工艺还可用于制作大功率MOSFET的栅介质,可提高器件的可靠性。     

带自适应斜坡补偿的COT控制Buck变换器

提出了一种采用自适应斜坡补偿(ARC)的恒定导通时间控制Buck变换器。引入了两个斜坡电压,实现对电感电流下降斜率的检测;通过负反馈环路调节斜坡斜率,使斜坡斜率跟随电感电流下降斜率的变化。最终斜坡补偿带来的额外极点被固定下来,以便于补偿设计。在此基础上,引入瞬态增强电路,提高了负载阶跃响应速度。在5 V输出电压下,负载从3 A到100 mA阶跃时,输出上冲电压减小了150 mV,恢复时间缩短了10 μs。负载从100 mA到3 A阶跃时,输出下冲电压减小了130 mV,恢复时间缩短了12 μs。     

3GPP IMS实时业务会话的无缝移动性方案

IP多媒体子系统(IM S)将给用户带来大量的实时多媒体应用,但目前3G PP IM S仅能支持游牧移动性,不支持无缝移动性,影响了IM S实时业务的用户体验。分析了IM S现有移动性机制的局限性,然后基于会话初始化协议(SIP)提出了一种适合IM S实时多媒体业务会话的无缝移动性方案,并与基于M IPv4的方案进行了对比,分析了该方案的优势。     

N_2和NH_3退火对铪铝氧栅介质C-V特性的影响

采用原子层淀积(ALD)的方法在Si(100)衬底上制备了铪铝氧(HfAlO)高介电常数介质,并研究了N2和NH3退火对于介质薄膜的影响。改变原子层淀积的工艺,制备了三组含有不同Al∶Hf原子比的铪铝氧(HfAlO)高介电常数介质。电容电压特性(C-V)测试表明,薄膜的积累电容密度随着薄膜中Al∶Hf原子比的减少而增加。实验表明,用N2和NH3对样品进行淀积后退火,可以减小等效电容厚度(CET)、降低固定正电荷密度以及减小滞回电压,从而有效地提高了介质薄膜的电学特性。     

超薄氮氧叠层栅介质的金属栅pMOS电容的电学特性

研究了高质量超薄氮化硅/氮氧化硅(N/O)叠层栅介质的金属栅pMOS电容的电学特性,制备了栅介质等效厚度小于2nm的N/O复合叠层栅介质,该栅介质具有很强的抗硼穿通能力和低的漏电流.实验表明这种N/O复合栅介质与优化溅射W/TiN金属栅相结合的技术具有良好的发展前景.     

低温下氮化硅膜的制备及特性的分析研究

本文阐述了等离子增强化学汽相淀积(PECVD)氮化硅膜的生长原理和方法;对于在不同衬底,如Si,特别是GaAs和金属膜上淀积氮化硅膜的各种影响因素进行了理论和实验分析;针对GaAs上淀积氮化硅膜的特殊现象提出了新的解释;推导出了SiN膜性能参数Si/N、折射率、Si-H键和N-H键密度等量之间关系的经验公式;研完了MNM电容上下电极对SiN性能的影响,指出用Ti-Pt-Au做下电极,Al做上电极可以提高电容耐压;确立了优化的条件,在较低温度(200～300℃)下生长出了氧含量极低、致密耐击穿电压高的优质SiN膜,该介质膜实用于半导体单片集成电路和高耐薄膜电容。     

电离辐射对Si_3N_4/SiO_2/Si双界面系统的作用

采用氩离子刻蚀XPS(X光激发电子能谱)分析对S i3N4/S iO2/S i双界面系统进行了电离辐照剖面分析。实验结果表明:电离辐照能将S iO2和S i构成的界面区中心向S i3N4/S iO2界面方向推移,同时S iO2/S i界面区亦被电离辐照展宽。在同样偏置电场中辐照,随着辐照剂量的增加电离辐照相当程度地减少位于S iO2/S i界面区S i3N4态(结合能B.E.101.8 eV)S i的浓度。同时辐照中所施偏置电场对S iO2/S i界面区S i3N4态键断开有显著作用。文中就实验现象的机制进行了初步探讨。     

引入a—Si：H材料的氮化硅芯片电容

本文研制了两种引入a-Si:H材料的氮化硅芯片电容,其一是作为辅助介质引入的,其二是为了改善Si/Si2N4界面而引入的,文章报导了这两种电容的研制工艺及样品的各种性能,其结构表明,这类电容有希望应用于厚薄膜集成电路.     

PECVD Si_xO_yN_z膜及其在GaAs VHSIC中的应用

采用SiH_4,N_2O和NH_3反应气体生长了Si_xO_yN_z膜,其特性取决于反应气体流量、射频功率、反应室压力和衬底温度。用折射率为1.71的Si_xO_yN_z做GaAs注Si~+包封退火膜,它比SiO_2或Si_3N_4有更高的电激活。该膜作为互连隔离介质已用于GaAs高速电压比较器。实验结果表明:Si_xO_yN_z是一种有希望的介质膜。     

Intrinsic and extrinsic reliability of a serial connection of capacitors

The on-wafer serial connection of two capacitors (stacked capacitors) is attractive for two reasons: on one hand the intrinsic reliability and especially the immunity against high voltage pulses increases and on the other hand the early fail risk decreases tremendously. The intrinsic and extrinsic reliability of stacked capacitors are demonstrated using the example of a metal insulator metal capacitor (MIMCAP) with Al₂O₃ dielectric. The intrinsic reliability of a stacked capacitor, where each of the capacitors uses a dielectric of thickness thk, is equal to the intrinsic reliability of a single capacitor with twice the dielectric thickness 2 * thk. The reduction of early fails for a stacked capacitor is a probability effect: if a single capacitor has the probability p to fail early and an early fail of the stacked capacitor is the combination of two single capacitors each of which contains an early fail, then the stacked capacitor fails early with a probability of p². This basic idea is checked by voltage ramp experiments on single and stacked MIM capacitors, where the single MIM capacitors show besides the intrinsic branch a prominent extrinsic branch.     

Analysis of reliability characteristics of high capacitance density MIM capacitors with SiO2-HfO2-SiO2 dielectrics

In this paper, reliability as well as electrical properties of high capacitance density metal-insulator-metal (MIM) capacitor with hafnium-based dielectric is analyzed in depth. The fabricated MIM capacitor exhibits not only high capacitance density but also low voltage coefficient of capacitance (VCC) and low temperature coefficient of capacitance (TCC). It also has a low leakage current level of about ∼1 nA/cm² at room temperature and 1 V. However, it is shown that voltage linearity has a different dependence on the polarity of applied bias as temperature increases maybe due to the bulk traps between the metal electrode and high-k dielectric interface. In addition, the effect of charge trapping and de-trapping on the voltage linearity is analyzed under constant voltage stress.     

Thermo-mechanical analysis and interfacial energy release rate estimation for metal-insulator-metal capacitor device

The metal-insulator-metal (MIM) capacitor device is the most popular structure that has been massively used in system circuit designs in IC and PCB processes. The characteristics of system will be changed and electrical performances will be impaired if large deformations are resulted in MIM capacitor device. Therefore, the concerns of reliability for MIM capacitor devices are very important issues. For the purpose of realizing the probability of delamination of GaAs/Si₃N₄ interface in MIM capacitor device, the four-point bend experiment is employed to evaluate the critical energy release rate, which is an important index to determine the possibility of inducing interfacial delamination. Moreover, to validate the phenomenon of delamination in MIM capacitor device, the finite element analysis (FEA) and modified virtual crack closure technique (MVCCT) are adopted. Thermo-mechanical stress distributions in MIM capacitor device that under reliability test conditions can be illustrated. The results show that the maximum stress occurs at the layer of Si₃N₄ or its corresponding interfaces. These stress concentration areas are critical places to be fractured. Furthermore, the designs of experiments (DOE) analysis is also employed to have better geometric parameters in MIM capacitor device to reduce stresses. It is believed that this study will be useful design guideline to prevent the phenomenon of interfacial delamination and enhance the reliability.     

氮化硅薄膜MIM电容器的制备与性能研究

在被釉氧化铝陶瓷基片上,采用真空电阻蒸发法和等离子体增强化学气相沉积法制备了Au/NiCr电极薄膜及氮化硅(SiNx)介质薄膜,并对薄膜进行光刻图形化,制成了Au/NiCr/SiNx/Au/NiCr结构的MIM电容器。研究了所制电容器的介电性能、介温性能和I-V特性等电学性能。结果表明:所得MIM电容器具有很低的介电损耗(1MHz时tanδ为0.00192)及很高的电压稳定性;在–55～+150℃的范围内其1MHz时的电容温度系数为258×10–6/℃;另外,其I-V特性曲线显示出较好的对称性,漏电流密度较低,可承受较高的电压。     

An Experimental Verification of a Simple Distributed Model of MIM Capacitors for MMIC Applications

A distributed model has been derived for MIM capacitors using a simple coupled-transmission-line approach. The model has been compared with measured S-parameter data from MIM capacitors having different aspect ratios fabricated on 4-mil GaAs substrates. The agreement is very good. The derived model will converge to the first-order capacitor model, generally given in the literature, under a few assumptions.     

Time dependent breakdown characteristics of parylene dielectric in metal–insulator–metal capacitors

In this work, we present reliability results of MIM (Metal–Insulator–Metal) capacitors fabricated with parylene as the dielectric, deposited at room temperature. We have evaluated the time dependent dielectric breakdown (TDDB) of parylene-based MIM capacitors as a function of constant DC voltage stress, area and dielectric thickness of the capacitor. Mean-time-to-failure (MTTF) of parylene evaluated at different stress voltages shows a power law distribution over the applied voltage range and device area, with MTTF driven by the number of defects. Defect density in the parylene capacitors is also reported and is calculated to be ～1.2 × 10³ defects/cm².     

新型低驱动电压电子纸显示单元的研究

研制了一种基于介质上电润湿(electrowetting-on-dielectric,EWOD)的新型低驱动电压电子纸反射式显示单元器件.本文分析了器件的工作原理以及性能影响因素,并提出用优化的氮化硅与碳氟聚合物复合介质层来改善器件的驱动电压.实验证实,器件在15V低电压驱动下成功实现了"开启"、"关闭"功能,其"开启"、"关闭"响应时间小于1/30s.     

A high performance MIM capacitor using HfO2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO₂ high-κ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (~200°C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO₂ MIM capacitor can provide a higher capacitance density than Si₃N₄ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2×10^-9 A/cm² at 3 V is achieved. All of these make the HfO ₂ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications     

High-Performance MIM Capacitors Using HfLaO-Based Dielectrics

Metal-insulator-metal (MIM) capacitors fabricated with (8%) La-doped HfO₂ single layer as well as HfLaO/ LaAlO₃/HfLaO multilayer dielectric stack are demonstrated. While the La-doped HfO₂ single layer is crystallized at 420^°C annealing, HfLaO/LaAlO₃/HfLaO multilayer dielectric stack remains amorphous. A high dielectric-constant value of 38 can be obtained when 8% La-doped HfO₂ is crystallized into cubiclike structure. However, it is observed that the linearity of MIM capacitor is degraded upon crystallization. The multilayer film has lower average dielectric constant but shows low quadratic voltage linearity of less than 1000 ppm/V² up to a capacitance density of 9 fF/?m² . It is observed that the HfLaO single-layer MIM is suitable for the applications with requirements of high capacitance density and robust reliability, while the multilayer MIM is suitable for a precision circuit.