Transition from the two- to three-dimensional growth of Ge films upon deposition onto relaxed SiGe/Si(001) buffer layers

The critical thickness of the two-dimensional growth of Ge on relaxed SiGe/Si(001) buffer layers different in Ge content is studied in relation to the parameters of the layers. It is shown that the critical thickness of the two-dimensional growth of Ge on SiGe buffer layers depends on the lattice mismatch between the film and the substrate and, in addition, is heavily influenced by Ge segregation during SiGe-layer growth and by variations in the growth-surface roughness upon the deposition of strained (stretched) Si layers. It is found that the critical thickness of the two-dimensional growth of Ge directly onto SiGe buffer layers with a Ge content of x = 11–36% is smaller than that in the case of deposition onto a Si (001) substrate. The experimentally detected increase in the critical thickness of the two-dimensional growth of Ge with increasing thickness of the strained (stretched) Si layer predeposited onto the buffer layer is attributed to a decrease in the growth-surface roughness and in the amount of Ge located on the surface as a result of segregation.     

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.     

Photoluminescence line width of self-assembled Ge(Si) islands arranged between strained Si layers

The effect of variations in the strained Si layer thicknesses, measurement temperature, and optical excitation power on the width of the photoluminescence line produced by self-assembled Ge(Si) nanoislands, which are grown on relaxed SiGe/Si(001) buffer layers and arranged between strained Si layers, is studied. It is shown that the width of the photoluminescence line related to the Ge(Si) islands can be decreased or increased by varying the thickness of strained Si layers lying above and under the islands. A decrease in the width of the photoluminescence line of the Ge(Si) islands to widths comparable with the width of the photoluminescence line of quantum dot (QD) structures based on direct-gap InAs/GaAs semiconductors is attained with consideration of diffusive smearing of the strained Si layer lying above the islands.     

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.     

Special features of the formation of Ge(Si) islands on the relaxed Si1−xGex/Si(001) buffer layers

The results of studying the growth of self-assembled Ge(Si) islands on relaxed Si_1?xGe_x/Si(001) buffer layers (x≈25%), with a low surface roughness are reported. It is shown that the growth of self-assembled islands on the buffer SiGe layers is qualitatively similar to the growth of islands on the Si (001) surface. It is found that a variation in the surface morphology (the transition from dome-to hut-shaped islands) in the case of island growth on the relaxed SiGe buffer layers occurs at a higher temperature than for the Ge(Si)/Si(001) islands. This effect can be caused by both a lesser mismatch between the crystal lattices of an island and the buffer layer and a somewhat higher surface density of islands, when they are grown on an SiGe buffer layer.     

Use of high order precursors for manufacturing gate all around devices

Epitaxial growth of strained and defect free SiGe layers grown with disilane and digermane was investigated. This precursors set allows to cover a broad range of Ge concentration (15–65%) at low temperatures (400–550 °C). It was shown that change of carrier gas (from H₂ to N₂) does not increase SiGe growth rate but significantly reduces Ge concentration. Increase of total process pressure considerably reduces SiGe growth rate which is attributed to peculiarities of digermane decomposition and influence of hydrogen surface passivation on disilane decomposition. It was shown that both disilane and digermane can be successfully combined with conventional precursors like silane and germane. These experiments suggested that digermane decomposition is the main driver of the growth rate increase during SiGe growth. Based on the presented data we demonstrated growth of different SiGe/Si and SiGe/Ge stacks with high quality necessary for production of gate all around field effect transistors.     

A study of the oxidation behavior and the postannealing effect in a graded SiGe/Si heterostructure

A study on the dry thermal oxidation of a graded SiGe layer was performed. To reduce the Ge pileup effect during the thermal oxidation, the SiGe layer was deposited with much lower Ge content near the free surface than near the SiGe/Si heterointerface. After dry thermal oxidation at 900°C, the Ge composition in the pileup layer was significantly reduced and strain relaxation by defect formation was prevented due to the graded Ge distribution. To homogenize the Ge distribution between the pileup layer and remaining SiGe layer, the oxidized layers were postannealed. The homogenization is significantly enhanced by strain-induced diffusion, and it was confirmed by uphill diffusion of Ge. This result can propose an alternative oxidation method of strained SiGe/Si heterostructures.     

Influence of surface roughness on a change in the growth mode from two-dimensional to three-dimensional for strained SiGe heterostructures

The influence of the surface microroughness on the critical thickness for the two-dimensional growth of strained SiGe structures on Si(001) and Ge(001) substrates is investigated. A decrease in the critical thickness for the two-dimensional growth of Ge films with increasing number of lattice periods or a decrease in the thickness of Si spacer layers is found for Ge/Si lattices grown on Si(001) substrates. This change is related to an increase in the surface roughness with the accumulation of elastic energy in compressed structures. A comparative study of the growth of SiGe structures on Si(001) and Ge(001) substrates shows that the critical thickness for the two-dimensional growth of tensile-strained layers is much larger than for compressed layers in a wide range of SiGe-layer compositions at an identical (in magnitude) lattice mismatch between the film and substrate.     

Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs

A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperature-dependent measurements are used to extract the phonon-limited mobility as a function of SiGe channel thickness for strained Si_0.57Ge_0.43 heterostructures on bulk Si. The hole mobility is shown to degrade significantly for channel thickness below 4 nm due to a combination of phonon and interface scattering. Due to the finite nature of the quantum-well barrier, SiGe film thickness fluctuation scattering is not significant in this structure for channel thickness greater than 2.8 nm.     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.     

The properties of Si/Si1-xGex films grown on Si substrates by chemical vapor deposition

A growth parameter study was made to determine the proper of a SiGe superlattice-type configuration grown on Si substrates by chemical vapor deposition (CVD). The study included such variables as growth temperature, layer composition, layer thickness, total film thickness, doping concentrations, and film orientation. Si and SiGe layers were grown using SiH₄ as the Si source and GeH₄ as the Ge source. When intentional doping was desired, diluted diborane for p-type films and phosphine for n-type films were used. The study led to films grown at ∼1000°C with mobilities from ∼20 to 40 percent higher than that of epitaxial Si layers and ∼100 percent higher than that of epitaxial SiGe layers grown on (100) Si in the same deposition system for net carrier concentrations of ∼8x10¹⁵ cm^-3 to ∼2x10¹⁷ cm^-3. Enhanced mobilities were found in multilayer (100)-oriented Si/Si_1-xGe_x films for layer thicknesses ≥400A, for film thicknesses >2μm, and for layers with x = 0.15. No enhanced mobility was found for (111)-oriented films and for B-doped multilayered (100)-orlented films. Supported in part by NASA-Langley Research Center, Hampton, VA, Contract NAS1-16102 (R. Stermer & A. Fripp, Contr. Mon.)     

Effect of growth temperature on photoluminescence of self-assembled Ge(Si) islands confined between strained Si layers

The effect of growth temperature on photoluminescence is studied for structures with Ge(Si) islands grown on relaxed SiGe/Si(001) buffer layers and confined between strained Si layers. It is shown that, with decreasing growth temperature in the range from 700 to 630°C, the photoluminescence peak associated with the islands shifts to lower energies, which is due to the increase in Ge content in the islands and to suppression of degradation of the strained Si layers. The experimentally observed shift of the photoluminescence peak to higher energies with decreasing temperature from 630 to 600°C is attributed to the change in the type of the islands from domelike to hutlike in this temperature range. This change is accompanied by an abrupt decrease in the average height of the islands. The larger width of the photoluminescence peak produced by the hut islands in comparison with the width of the peak produced by the domelike islands is interpreted as a result of a wider size dispersion of the hutlike islands.     

Resonant cavity enhanced photoluminescence of tensile strained Ge/SiGe quantum wells on silicon-on-insulator substrate

The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photoluminescence from Ge quantum wells on SOI substrate is strongly modulated by Fabry-Perot cavity formed between the surface of Ge and the interface of buried SiO2. The photoluminescence peak intensity at 1.58 μm is enhanced by about 21 times compared with that from the Ge/SiGe quantum wells on Si substrate, and the full width at half maximum （FWHM） is significantly reduced. It is suggested that tensile strained Ge/SiGe multiple quantum wells are one of the promising materials for Si-based microcavity lijzht emitting devices.     

RPCVD生长SiGe薄膜及其性能研究

利用应用材料公司外延设备,在Si(001)衬底上,通过RPCVD方式生长出完全应变、无位错的SiGe外延层.通过X射线衍射和原子力显微镜测试技术,得到了外延层Ge摩尔分数、外延层厚度、生长速率以及表面粗糙度等参数,研究了运用RPCVD方法制备的应变SiGe外延层的生长特性以及薄膜特性.结果表明,在660℃所生长的薄膜,其XRD图像均出现了Pendelossung条纹,表明薄膜质量较好.Ge摩尔分数高达16.5%.薄膜表面粗糙度RMS在0.3～0.6nm.     

Si1-xGex/Si应变材料的生长及热稳定性研究

利用分子束外延（MBE）技术生长了Ge组份为0.1-0.46的Si1-xGex外延层。X射线衍射线测试表明，SiGe/Si异质结材料具有良好的结晶质量和陡峭界面，其它参数与可准确控制。通过X射线双晶衍射摆曲线方法，研究了经700℃、800℃和900℃退火后应变SiGe/Si异质结材料的热稳定性。结果表明，随着退火温度的提高，应变层垂直应变逐渐减小，并发生了应变弛豫，导致晶体质量退化；且Ge组分越小，Si1-xGex应变结构的热稳定性越好；室温下长时间存放的应变材料性能稳定。     

应变p型Si1-xGex层中载流子冻析

本文用解析的方法研究了应变Ｐ型Ｓｉ１－ｘＧｅｘ层中载流子冻析现象，研究发现，用Ｓｉ归一化的Ｓｉ１－ｘＧｅｘ价带有效态密度、随ｘ的增加而减小，而且温度Ｔ越低，随Ｇｅ组份ｘ的增加而减少的速度越快，与Ｓｉ相比，常温下Ｇｅ组份ｘ几乎对电离 杂质浓度没有什么影响，而在低温下，随Ｇｅ组份ｘ的增加，电离杂质浓度随之增加，载流子冻析减弱，这对低温工作的Ｓｉ１－ｘＧｅｘ器件有利。     

Thermally Processed High-Mobility MOS Thin-Film Transistors on Transferable Single-Crystal Elastically Strain-Sharing Si/SiGe/Si Nanomembranes

Demonstration of high-performance MOS thin-film transistors (TFTs) on elastically strain-sharing single-crystal Si/SiGe/Si nanomembranes (SiNMs) that are transferred to foreign substrates is reported. The transferable SiNMs are realized by first growing pseudomorphic SiGe and Si layers on silicon-on-insulator (SOI) substrates, and then, selectively removing the buried oxide (BOX) layer from the SOI. Before the release, only the SiGe layer is compressively strained. Upon release, part of the compressive strain in the SiGe layer is transferred to the thin Si layers, and the Si layers, thus, become tensile strained. Both the initial compressive strain state in the SiGe layer and the final strain sharing state between the SiGe and the Si layers are verified with X-ray diffraction measurements. The TFTs are fabricated employing the conventional high-temperature MOS process on the strain-shared SiNMs that are transferred to an oxidized Si substrate. The transferred strained-sharing SiNMs show outstanding thermal stability and can withstand the high-temperature TFT process on the new host substrate. The strained-channel TFTs fabricated on the new host substrate show high current drive capability and an average electron effective mobility of 270 cm²/V ldr s. The results suggest that transferable and thermally stable single-crystal elastically strain- sharing SiNMs can serve as excellent active material for high-speed device application with a simple and scalable transfer method. The demonstration of MOS TFTs on the transferable nanomembranes may create the opportunity for future high-speed Si CMOS heterogeneous integration on any substrate.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

深亚微米应变SiGe沟PMOSFET特性模拟

为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si Ge沟PMOSFET具有很大的性能提高潜力     

Studies on the growth of CdTe on Si using ge interfacial layer in an organometallic vapor phase epitaxial system

Epitaxial CdTe layers were grown using organometallic vapor phase epitaxy on Si substrates with a Ge buffer layer. Ge layer was grown in the same reactor using germane gas and the reaction of germane gas with the native Si surface is studied in detail at low temperature. It is shown that germane gas can be used to “clean” the Si surface oxide prior to CdTe growth by first reducing the thin native oxide that may be present on Si. When Ge layer was grown on Si using germane gas, an induction period was observed before the continuous layer of Ge growth starts. This induction period is a function of the thickness of the native oxide present on Si and possible reasons for this behavior are outlined. Secondary ion mass spectrometry (SIMS) data show negligible outdiffusion and cross contamination of Ge in CdTe.