Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

信号流驱动的模拟电路版图综合方法

提出了一种新的基于信号流分析的模拟电路版图综合方法.电路分析子系统采用新提出的信号流分析方法再结合已有的电路拓扑分析和电路灵敏性分析方法生成布图约束控制电路性能的衰减.由于考虑了电路中有关信号流的启发式信息,该方法的复杂性较一般的纯粹性能驱动方法小.然后分别在器件生成子系统、布图子系统和布线子系统中实现这些约束,使得这些约束在最容易实现的阶段得到满足.实际的电路例子已经证明了这一方法可以获得出色的电路性能.     

A Signal-Flow Driven Automatic Physical Synthesis Methodology for Analog Circuits

This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signalflow，complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement，and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.     

模拟集成电路版图中的对称检测与提取方法

新一代模拟集成电路版图自动化系统在重用原有版图时,迫切需要提取其中的匹配设计信息,以保证其输出版图的质量.在角勾链数据结构的基础上,提出了新的对称检测、提取算法及数据结构.该算法检测出器件之间的对称关系,进一步提取出模块之间的对称关系,并将器件级和模块级对称关系及底层的角勾链结构以独特的数据结构统一存储.结果表明,该算法与数据结构能够有效地提取并表示设计者在版图中渗透的匹配设计思想,为版图的生成提供多级对称约束条件,从而有力地保证重用系统所输出的模拟版图的性能.     

一种增益可控音频前置放大器电路的设计

设计了一种基于0.5μm CMOS工艺的增益可控音频前置放大器电路。该电路采用直流音量控制方式控制前置放大器的增益,进而实现整体音频放大器的音量控制。外部输入的直流模拟电压经过片内模数转换器转换成数字控制信号,控制前置放大器的输入电阻与反馈电阻的比值,从而实现前置放大器的增益控制。该放大器能够实现32档的音量控制范围,增益从-50 dB变化到25 dB,电路版图面积为1.2 mm×0.8 mm。     

A technology-independent approach to custom analog cell generation

STAT (schematic to artwork transistor), a set of software tools designed to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology, is described. The system enables the circuit designer to annotate the schematic with component matching and symmetry relationships. Software subroutines are then used to generate device artwork. The placement program implements algorithms in which groups of related components are placed first so that annotated layout constraints are preserved. A novel placement method is offered which recognizes that analog schematic topologies often reflect desirable layout configurations. A flexible multilayer cell-level router has been developed to complete the device interconnection. The STAT system functions in either a polygon or symbolic layout environment. The symbolic layout allows design-rule and technology changes to be made easily and is designed to interface with a commercial compaction program to produce the final layout     

SDW MOSFETs in LSI analog circuit design

Single-device-well (SDW) MOSFETs are based on merging two devices-a surface and a buried MOSFET to share the same device well and the same gate. They offer flexible circuit structures in the design of LSI analog circuit blocks with a circuit area saving which ranges typically from 30-60 percent. The authors discuss in detail the design and the analysis of SDW source followers and difference stages. It also gives examples of SDW circuit configurations for current sources, potential dividers, and output stages.     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性 .提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及 STACK内连线的不匹配的模型 .基于该模型 ,一种新的 STACK生成方法用来控制版图的寄生参数和匹配特性 ,优化 STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图 .一个 OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能     

带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性．提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及STACK内连线的不匹配的模型．基于该模型,一种新的STACK生成方法用来控制版图的寄生参数和匹配特性,优化STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图．一个OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能．     

S－域行为描述的模拟集成电路综合方法

本文提出了一种通用的、从Ｓ－域传输函数入手进行模拟集成电路结构级综合的方法，并详细地讨论了提高电路性能和合格率的电路技巧。此外，本文还给出了生成物理版图的一点建议，本文采用该方法完成了切比雪夫滤波器的综合，ＳＰＩＣＥ模拟结果表明该方法是可行的。     

Integration of VLSI circuits and mechanics for vibration control of flexible structures

The approach to modeling and control of smart flexible structures presented in this paper is based on the concept that an intelligent structure requires an internal knowledge of self to act intelligently. This knowledge can be acquired from local analog models of substructure dynamics and can be used in model-based controller designs. The key to this approach is the synergistic integration of analog VLSI circuit models and control with the sensing and actuation which are then to be embedded into the mechanical structure. This paper presents the motivation, development, and test results of analog VLSI circuit models for use in model-based control of smart flexible structures. Furthermore, control applications for these VLSI circuits are developed and simulation results are presented in which the VLSI circuits are used in adaptive vibration control of a simple mass-spring system.     

Statistical modeling of device mismatch for analog MOS integratedcircuits

A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms     

数模混合电路实现一维模拟小波变换芯片

整个电路采用标准CMOS工艺,采取模块化设计的方法,把数字频率发生器和模拟滤波器部分分开设计。数字频率发生器采用直接数字综合(DDS)的方式,来产生5种不同中心频率(10个通道),简化了传统模拟压控振荡器(VCO)的设计,提高了频率发生器的灵活性;根据精度要求,模拟高斯低通滤波器采用5阶低通滤波器来进行逼近。并论述和讨论了一种用数字和模拟混合集成电路来实现一维模拟输入的连续小波变换(CWT)芯片的方法。     

一种单刀双掷高速模拟开关的研制

介绍了一种单刀双掷高速模拟开关;描述了电路工作原理、线路设计、版图设计及可靠性设计。该高速模拟开关具有速度快、功耗低、隔离度高、关断漏电流小等特点。其内部电路设计有控制输入级、电平转换级、高速模拟开关管及静电保护电路。该电路可广泛应用于雷达接收机和发射机、通信系统和数据采集系统,以及通用模拟开关等领域。