基于等离子体氮化工艺的超薄栅氧化膜的电学特性和可靠性

介绍了利用MMT等离子体氮化工艺和炉管NO退火氮化工艺制备的超薄栅介质膜的电学特性和可靠性.结合两种氮化工艺在栅介质膜中形成了双峰和单峰的氮分布.通过漏极电流、沟道载流子和TDDB的测试,发现栅介质膜中双峰的氮分布可以有效提高器件的电学特性,更为重要的是可以极大提高器件的击穿特性.这指明了延长掺氮氧化膜在超大规模集成电路器件栅介质层中应用的寿命,使之有可能进一步跟上技术的发展.     

超薄LPCVD二氧化硅膜栅介质

本文介绍低温生长的薄LPCVD二氧化硅膜经短时间热退火后，热氮化后的物理及电学性质。与热生长二氧化硅膜性质进行比较，结果表明，LPCVD二氧化硅膜许多性质优于热生长二氧化硅膜。适合做MOS晶体管的栅介质。文中重点指出，小于10nm的超薄的LPCVD二氧化硅膜经快速热退火或热氮化后做MOS晶体管的栅介质，其电学特性优于热生长二氧化硅膜做栅介质的MOS晶体管。在低温器件及超大规模集成电路中有广泛的应用前景。     

栅介质氧化层缺失缺陷的形成原因及解决方案

氮氧化技术是45 nm及以下技术节点栅介质制备的关键工艺,严格控制由氮氧化工艺所诱发的界面缺陷是提高栅介质质量的重点.研究了形成栅介质氧化层缺失缺陷的原因,并提出了解决方案.结果表明,原位水蒸气生成(ISSG)热氧化形成栅介质氧化层后的实时高温纯惰性氮化热处理工艺是形成栅介质氧化层缺失缺陷的主要原因;在实时高温纯惰性氮化热处理工艺中引入适量的O2,可以消除栅介质氧化层的缺失缺陷.数据表明,引入适量O2后,栅介质氧化层的界面陷阱密度(Dit)和界面总电荷密度(ΔQtot)分别减少了12.5％和26.1％;pMOS器件负偏压不稳定性(NBTI)测试中0.1％样品失效时间(t0.1％)和50％样品失效时间(t50％)分别提高了18％和39％;32 MB静态随机存储器(SRAM)在正常工作电压和最小工作电压分别提高了9％和13％左右.     

离子注入氮化薄SiO2栅介质的特性

研究了通过多晶硅栅注入氮离子氮化10nm薄栅SiO2的特性.实验证明氮化后的薄SiO2栅具有明显的抗硼穿透能力,它在FN应力下的氧化物陷阱电荷产生速率和正向FN应力下的慢态产生速率比常规栅介质均有显著下降,氮化栅介质的击穿电荷(Qbd)比常规栅介质提高了20%.栅介质性能改善的可能原因是由于离子注入工艺在栅SiO2中引进的N+离子形成了更稳定的键所致.     

离子注入氮化薄SiO_2栅介质的特性

研究了通过多晶硅栅注入氮离子氮化 10 nm薄栅 Si O2 的特性 .实验证明氮化后的薄 Si O2 栅具有明显的抗硼穿透能力 ,它在 FN应力下的氧化物陷阱电荷产生速率和正向 FN应力下的慢态产生速率比常规栅介质均有显著下降 ,氮化栅介质的击穿电荷 (Qbd)比常规栅介质提高了 2 0 % .栅介质性能改善的可能原因是由于离子注入工艺在栅 Si O2 中引进的 N+离子形成了更稳定的键所致     

直接热氮化SiO2薄膜的电特性

对热生长SiO_2膜,在NH_3气氛中高温退火所形成的热氮化SiO_2薄膜是一种有希望用于VLSI工艺的介质膜。本文采用多种方法,较为全面地分析了不同氮化条件下这种薄膜的界面特性、介电性能、电子陷阱参数、掩蔽杂质扩散能力等电学特性;并用其做为绝缘栅制成MOSFET。讨论了热氮化对阈电压和表面电子迁移率的影响。     

离子注入氮化薄SiO2栅介质的特性

研究了通过多晶硅栅洲入氮离子氮化10nm薄栅SiO2的特性,实验证明氮化后的薄SiO2栅具有明显的抗硼穿透能力,它在FN应力下的氧化物陷阱电荷产生速率和正向FN应力下的慢态产生速率比常规栅介均有显下降,氮化栅介质的击穿电荷（Qbd)比常规栅介质提高了20％,栅介质性能的可能原因是由于离子注入工艺在栅SiO2中引进的N^ 离子形成了更稳定的键所致。     

DLTS技术研究富氮SiOxNy薄介质膜的电学特性

采用深能级瞬态谱技术（ＤＬＴＳ）,测试了等离子体增强化学汽相淀积（ＰＥＣＶＤ）法低温制备的富氮的ＳｉＯｘＮｙ栅介质膜的电学特性（界面态密度、俘获截面随禁带中能量的变化关系）,结果表明,采用合适的ＰＥＣＶＤ低温工艺淀积ＳｉＯｘＮｙ膜可以制备性质优良的栅介质膜。     

基于原位水汽生成的超薄栅氧膜电学特性研究

介绍了针对利用原位水汽生成工艺制作的超薄栅介质膜的电学特性研究.通过电荷泵和栅极隧穿漏电流的测试,证明了原位水汽生成工艺相比传统炉管氧化工艺能够有效地提高界面态特性,这种电学特性上的提高被认为与活性氧原子的氧化机制有关.同时,通过测试还发现提高生长温度和减小H2在反应气体中的比重可以获得更好的电特性,这也指明了原位水汽生长工艺存在进一步提高的可能.     

氮化H2-O2合成薄栅介质的击穿特性

研究了14～16nm的H2-O2合成薄栅介质击穿特性.实验发现,N2O气氛氮化H2-O2合成法制备的薄栅介质能够有效地提高栅介质的零时间击穿特性.H2-O2合成法制备的样品,其击穿场强分布特性随测试MOS电容面积的增加而变差,而氮化H2-O2合成薄栅介质的击穿特性随测试MOS电容面积的增加基本保持不变.对于时变击穿,氮化同样能够明显提高栅介质的击穿电荷及其分布.     

Modeling boron diffusion in ultrathin nitrided oxide p+Si gate technology

Based on a network defect model for the diffusion of B in SiO₂, we propose that B diffuses via a peroxy linkage defect (pld) whose concentration in the oxide changes under different processing conditions. We show that as N is added to the gate oxide (nitridation), N atoms compete with B atoms for activation through the diffusion-defect sites. The model predicts that nitridation is ineffective in stopping B penetration when BF₂ implants dope the polysilicon gate, as well as for the case of very thin gate dielectrics with B-implanted gates     

多晶硅后热退火引起SiO_2栅介质可靠性下降的原因分析及其抑制方法

实验研究表明 ,多晶硅后的高温退火明显引起热 Si O2 栅介质击穿电荷降低和 FN应力下电子陷阱产生速率增加 .采用 N2 O氮化则可完全消除这些退化效应 ,而且氮化栅介质性能随着退火时间增加反而提高 .分析认为 ,高温退火促使多晶硅内 H扩散到 Si O2 内同 Si— O应力键反应形成 Si— H是多晶硅后 Si O2 栅介质可靠性退化的主要原因 ;氮化抑制退化效应是由于 N “缝合”了 Si O2 体内的 Si— O应力键缺陷 .     

Post poly-Si gate rapid thermal nitridation for boron penetrationreduction and oxide reliability improvement

Boron penetration from p⁺ doped poly-Si gates in PMOSFET is greatly reduced by post poly-Si gate rapid thermal nitridation. Gate oxide reliability against boron penetration is significantly enhanced. When post poly-Si nitridation is combined with N ₂O annealed gate oxides, gate oxide charge-to-breakdown is markedly improved     

High-quality ultrathin (1.6 nm) nitride/oxide stack gatedielectrics prepared by combining remote plasma nitridation and LPCVDtechnologies

Ultrathin nitride/oxide (N/O) gate dielectric stacks with equivalent oxide thickness of 1.6 nm have been fabricated by combining remote plasma nitridation (RPN) and low pressure chemical vapor deposition (LPCVD) technologies. NMOSFETs with these gate stacks exhibit good interface properties, improved subthreshold characteristics, low off-state currents, enhanced reliability, and about one order of magnitude reduction in gate leakage current to their oxide counterparts     

Effective Work Function Engineering of TaxCy Metal Gate on Hf-Based Dielectrics

This letter reports the engineering of effective work function (EWF) for tantalum carbide (TaC) metal gate on high-k gate dielectrics. The dependence of EWF on Si concentration in HfSiO as well as nitridation techniques is revealed. The EWF was extracted by both terraced oxide and terraced high-k techniques with the bulk and interface charges taken into account. The incorporation of Si in Hf-based dielectrics results in an increase of EWF, while the presence of N tends to decrease the EWF. Plasma nitridation is found to be more effective in lowering the EWF than a thermal nitridation. The phenomena can be explained by the modification of TaC/high-k interface dipole moment, which arises from the electronegativity difference for various interface bonds. Based on the above findings, we proposed a novel approach to reduce the EWF of TaC on HfSiON by using a thin HfO₂ cap layer after optimizing the nitridation. The MOSFET results show that this technique is able to achieve a lower V_t without degrading the device performance     

ISSG及其氮化工艺对NBTI效应的改善

本文在对ISSG工艺特性简单分析的基础上讨论了ISSG氧化物薄膜的可靠性问题。讨论了ISSG工艺及其相关的氮化工艺对NBTI的改善原理。数据表明ISSG工艺及其相关的氮化工艺对NBTI效应有明显的改善作用。由于原子氧的强氧化作用,ISSG工艺中最终得到的氧化物薄膜体内缺陷少,界面态密度也比较小,氧化物薄膜的质量比较高。ISSG氮化工艺与传统炉管氧化物薄膜的氮化工艺的主要区别在于N所集中的位置不一样。ISSG工艺氮化是把等离子态的N^＋注入到多晶硅栅和SiQ2的界面,不会增加SiQ2和Si衬底的界面态,从而可以显著改善NBTI效应。而传统炉管氧化物薄膜的氮化是用NO或者N2O把N注入到SiQ2和Si衬底的界面,这样SiQ2和Si的界面态就会增加,从而增强NBTI效应。     

Random telegraph signal: A sensitive and nondestructive tool for gate oxide single trap characterization

This paper presents the electrical characterization of thick and thin SiO₂ oxynitride performed by thermal and plasma nitridation processes. The impact of the nitridation technique is investigated using random telegraph signal (RTS) noise analysis. The variation of the gate oxide trap characteristics is determined with respect to the nitridation technique. Significant properties of traps are also pointed out. Main trap parameters, such as their depth with respect to the interface, nature, capture and emission times are extracted. These results illustrate the potential of RTS noise investigation for gate oxide characterizations.     

The effect of remote plasma nitridation on the integrity of theultrathin gate dielectric films in 0.13 μm CMOS technology and beyond

The authors report the effect of the remote plasma nitridation (RPN) process on characteristics of ultrathin gate dielectric CMOSFETs with the thickness in the range of 18 Å~22 Å. In addition, the effect of RPN temperature on the nitrogen-profile within the gate dielectric films has been investigated. Experimental results show that the thinner the gate dielectric films, the more significant effect on reducing the gate current and thinning the thickness of gate dielectric films by the RPN process. Furthermore, the minimum dielectric thickness to block the penetration of B and N has been estimated based on the experimental results. The minimum RPN gate dielectric thickness is about 12 Å     

Furnace nitridation of thermal SiO2 in pureN2O ambient for ULSI MOS applications

Furnace nitridation of thermal SiO₂ in pure N₂ O ambient for MOS gate dielectric application is presented. N₂O-nitrided thermal SiO₂ shows much tighter distribution in time-dependent dielectric breakdown (TDDB) characteristics than thermal oxide. MOSFETs with gate dielectric prepared by this method show improved initial performance and enhanced device reliability compared to those with thermal gate oxide. These improvements are attributed to the incorporation of a small amount of nitrogen (~1.5 at.%) at the Si-SiO₂ interface without introducing H-related species during N₂O nitridation