A clock feedthrough reduction circuit for switched-current systems

A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20%     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A low-noise CMOS instrumentation amplifier for thermoelectricinfrared detectors

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-μm single-poly n-well CMOS process. It features a gain of 52 dB with a 500 Hz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The equivalent input low frequency noise is 15 nV/√Hz. The typical residual input offset is 1.5 μV. The amplifier power consumption is 1.3 mW     

Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digitalbipolar technology

This paper describes the design of an all-npn open-loop sample-and-hold amplifier intended for use at the front end of analog-to-digital converters. Configured as a quasidifferential topology, the circuit employs capacitive coupling between the input and output to achieve differential voltage swings of 3 V in a 3.3-V system. It also exploits the high speed of bipolar transistors to attain a sampling rate of 100 MHz with a power dissipation of 10 mW. A prototype fabricated in a 1.5-μm 12-GHz digital bipolar technology exhibits harmonics 60 dB below the fundamental with a 10-MHz sinusoidal input. The hold-mode feedthrough is less than -60 dB and the droop rate is 100 μV/ns     

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm². The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns     

An accurate CMOS sample-and-hold circuit

An accurate sample-and-hold (S/H) circuit implemented with a 2-μm double-poly CMOS process is described. Competitive performance in terms of output swing, linearity, and clock feedthrough compensation was obtained using a new circuit topology. The sample and hold operates up to 1 MHz of sampling frequency with less than -60 dB of total harmonic distortion. The accuracy of the held step is better than 0.2 mV. The circuit dissipates 4 mW with a 5-V power supply     

A 14-bit dual-path 2-0 MASH ADC with dual digital error correction

A dual-path 2-0 cascaded delta-sigma (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The digital correction techniques greatly reduced the requirements on the analog circuits. The dual-path structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18 μm process.     

A time digitizer CMOS gate-array with a 250 ps time resolution

A pipelined time digitizer CMOS gate-array has been developed using 0.5 μm Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion     

A 6-GHz integrated phase-locked loop using AlGaAs/GaAsheterojunction bipolar transistors

A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking range was measured to be greater than 750 MHz at zero steady-state phase error. The nonaided acquisition range is approximately 300 MHz. This circuit is the first monolithic HBT PLL and is the fastest yet reported using a digital output VCO. The minimum emitter area was 3 μm×10 μm with f_t=22 GHz and f_max=30 GHz for a bias current of 2 mA. The speed of the PLL can be doubled by using 1-μm×10-μm emitters in next-generation circuits. The chip occupies a die area of 2-mm×3-mm and dissipates 800 mW with a supply voltage of -8 V     

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an accesstime of 550 ps and an operating frequency of 900 MHz

This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-μm MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 34%. Moreover, a variable-impedance load has been proposed to reduce cycle time. A 1-Mb ECL-CMOS SRAM was developed by using these circuit techniques and 0.2-μm BiCMOS technology. The fabricated SRAM has an ultrafast access time of 550 ps and a high operating frequency of 900 MHz with a power dissipation of 43 W     

Four-phase power clock generator for adiabatic logic circuits

A circuit for a four-phase trapezoidal power clock generator for adiabatic logic circuits realised with a double-well 0.25 μm CMOS technology and external inductors is proposed. The circuit, at a frequency of 7 MHz which is within the optimum frequency range for adiabatic circuits realised with 0.25 μm CMOS technology, has a conversion efficiency higher than 80%, and is robust with respect to parameter variations     

A 3.3 V, 10 Bits, Clock-Feedthrough Compensated Switched-Current Second Order Sigma-Delta Modulator

This article presents a low-pass sigma-delta modulator for Analogue-to-Digital conversion. The circuit uses a switched-current technique which presents a well known drawback called clock feedthrough. This phenomenon induces an error on the output signal value. In order to cancel the clock feedthrough effect, we use a new method based on a current feedback loop. The circuit is designed in 0.8 μm AMS “Austria Mikro Systems” single poly CMOS process. Measurements of the modulator are performed under A/D converters characterisation system, and show 55 dB dynamic range at 2.048 MHz sampling rate with 8 kHz input frequency bandwidth. These characteristics are suitable for audio applications.     

CMOS high-frequency switched-capacitor filters fortelecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use in a switched digital video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84 MHz (f_s =2f_clock=103.68 MHz for double sampling) while the three desired low-pass corner frequencies (f_c) are 8,12, and 20 MHz. The double-sampling, bilinear, elliptic, fifth-order switched-capacitor filter meets the desired -40-dB attenuation at 1.3 f _c, and -30 dB at 1.25 f_c. For the 12-MHz corner frequency setting, given the 2V_pp differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB. The analog power dissipation is 125 mW from a 5-V power supply. The test results indicate that the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype IC's are fabricated in a 0.35-μm 5-V (0.48 μm drawn) CMOS process     

2 Gbit/s transimpedance amplifier fabricated by 0.35 μm CMOStechnologies

Integrated CMOS transimpedance (TZ) amplifier circuits have been designed and fabricated based on a home-made BSIM model. A 0.35 μm CMOS technology was used for circuit realisation, and a capacitive-peaking design to improve the bandwidth of the TZ amplifier is proposed and investigated. Using this approach provides an easy way to improve the performance of the TZ amplifier; the measured 3 dB bandwidth is enhanced from 875 MHz to 1.35 GHz. The CMOS TZ amplifier design achieves a 2 Gbit/s data rate     

A 2.7-V 300-MS/s track-and-hold amplifier

A fully differential bipolar track-and-hold amplifier (THA) employs an open-loop linearization technique compatible with low supply voltage. A feedthrough reduction method utilizes the junction capacitance of a replica switch to provide a close match to the junction capacitance of the main switch. The differential full-scale (FS) input range is 0.5 V. In the track mode, with f_in=10 MHz, FS sinewave input, the measured total harmonic distortion (THD) is less than -72 dB. With f_s=300 MS/s and f_in=10-50 MHz, FS sinewave input, the measured THD is less than -65 dB. This THD measurement reflects the held values as well as the tracking components of the output waveform. With f_s<10 MS/s and f_in=10-50 MHz, FS sinewave input, the measured feedthrough is less than -60 dB. The hold capacitance is 2.5 pF and the differential droop rate is 16 mV/μs. The THA consumes 32 mW from a 2.7-V power supply and is fabricated in a 0.5-μm, 18-GHz BiCMOS process     

A 15-ns 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration has been developed. The RAM was fabricated using 0.8-μm double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic gain control sense amplifier combined with an equalization technique and feedback capacitances. A low active current of 50 mA at 20 MHz and low standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained     

Low-voltage dynamic BiCMOS CLA circuit with carry skip using novelfull-swing logic

This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known “MOS clock feedthrough effect” is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-μm BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-μm V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies     

Improved clock buffer with high PSRR for SC circuit applications

Clock feedthrough in SC circuits results in low PSRR figures, incompatible with high-performance signal processing. A high-PSRR CMOS clock buffer is presented here, which blocks this power supply (PS) noise coupling path. The presented circuit is a significant improvement over an earlier circuit proposed by the same author, but having a PSRR of over 40 dB now.<>     

An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributedtrack-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm² in 0.5-μm standard digital CMOS technology     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm