Electrical characteristics of ZrN metallised metal-oxide-semiconductor and metal-insulator-metal devices

The electrical properties of DC reactive sputtered zirconium-nitride metallized metal-oxide-semiconductor (MOS) and metal-insulator-metal (MIM) devices on TiO₂/p-Si and TiO₂/ZrN films were studied using capacitance-voltage (C-V) and current-voltage (I-V) measurements at room temperature. Capacitances of the ZrN/TiO₂/p-Si MOS device were measured in accumulation mode and inversion mode, from which flat band capacitance was found to be 2.86pF, which corresponds to flat band voltage of −1.7 V. Fixed oxide charged density and interface state density was found to be 1.63× 10¹⁰ cm⁻² and 6.3× 10¹¹ cm⁻² eV⁻¹. I-V characteristics revealed that the leakage current density was of 0.5 mA/cm² in accumulation mode and 2 mA/cm² in inversion mode at a field of 0.12 MV/cm, respectively. Dielectric breakdown of ZrN/TiO₂/p-Si device was found to be 0.12 MV/cm in accumulation mode. Based on the C-V and I-V characteristics, the ZrN/TiO₂/ZrN structure showed no variation in the capacitance value as the bias voltage was changed.     

Substrate bias voltage influenced structural, electrical and optical properties of dc magnetron sputtered Ta2O5 films

Tantalum oxide (Ta₂O₅) films were formed on silicon (111) and quartz substrates by dc reactive magnetron sputtering of tantalum target in the presence of oxygen and argon gases mixture. The influence of substrate bias voltage on the chemical binding configuration, structural, electrical and optical properties was investigated. The unbiased films were amorphous in nature. As the substrate bias voltage increased to −50 V the films were transformed into polycrystalline. Further increase of substrate bias voltage to −200 V the crystallinity of the films increased. Electrical characteristics of Al/Ta₂O₅/Si structured films deposited at different substrate bias voltages in the range from 0 to −200 V were studied. The substrate bias voltage reduced the leakage current density and increased the dielectric constant. The optical transmittance of the films increased with the increase of substrate bias voltage. The unbiased films showed an optical band gap of 4.44 eV and the refractive index of 1.89. When the substrate bias voltage increased to −200 V the optical band gap and refractive index increased to 4.50 eV and 2.14, respectively due to the improvement in the crystallinity and packing density of the films. The crystallization due to the applied voltage was attributed to the interaction of the positive ions in plasma with the growing film.     

Electrical properties of Ta2O5 films deposited on ZnO

High dielectric constant (high-k) Ta₂O₅films have been deposited on ZnO/p-Si substrate by microwave plasma at 150°C. Structure and composition of the ZnO/p-Si films have been investigated by X-ray diffraction (XRD), atomic force microscopy (AFM), scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) for chemical composition. The electrical properties of the Ta₂O₅/ZnO/p-Si metal insulator semiconductor (MIS) structures were studied using high frequency capacitance-voltage (C-V), conductance-voltage (G-V) and current-voltage (I-V) characteristics. Charged trapping properties have been studied by measuring the gate voltage shift due to trapped charge generation under Fowler-Nordheim (F-N) constant current stressing.     

Suppression of electrical breakdown in silicon nitride films deposited by catalytic chemical vapor deposition at temperatures below 200 degrees C

Silicon nitride (SiN(x)) films for a gate dielectric layer of thin film transistors were deposited by catalytic chemical vapor deposition at a low temperature (< or = 200 degrees C). A mixture of SiH4, NH3 and H2 was used as a source gas. Metal-insulator-semiconductor (MIS) capacitor structures were fabricated for current-voltage (I-V) and capacitance-voltage (C-V) measurements. The breakdown voltage characteristics of the SiN(x) films were improved by the increase of NH3/SiH4 and H2/SiH4 mixing ratios and substrate temperatures. H2 treatment was attempted to improve the breakdown voltage further. A breakdown voltage as high as 6.6 MV/cm was obtained after H2 annealing at 180 degrees C. The defect states inside the SiN(x) films were analyzed by photoluminescence spectra. Silicon dangling bonds (2.5 eV) and nitrogen dangling bonds (3.1 eV) were observed. These defect states inside the SiN(x) films disappeared after H2 annealing. Flat band voltage shifts were observed in C-V curves, and their magnitudes decreased as the defect states inside the SiN(x) films decreased.     

双层复合栅介质膜的制备及电学性能研究

介电常数分别为2.6的聚甲基丙烯酸甲酯(PMMA)及介电常数为16的偏氟乙烯-三氟乙烯共聚物(P(VDF-TrFE))两种不同的有机绝缘材料,通过溶液旋涂的方法在P型硅衬底上制备了不同结构的复合栅介质膜并测试了它们的高频C-V特性及漏电特性。实验结果表明Si-PMMA-P(VDF-TrFE)-Ag结构绝缘膜上单位面积电容达到了35nF/cm2,40V电压下漏电流随着扫描次数的增加逐渐由7.29×10-7 A/cm2降低至3.44×10-7 A/cm2。而Si-P(VDF-TrFE)-PM-MA-Ag结构栅介质膜测得的单位面积电容仅为15nF/cm2,在相同电压下的单位面积漏电流为1.93×10-8 A/cm2。在此基础上分析了电子陷阱以及电场强度对双层栅绝缘膜C-V、I-V特性的影响。     

Synthesis of SiOF nanoporous ultra low-k thin film

In this work, we have investigated the effect of annealing temperature on physical, chemical and electrical properties of Fluorine (F) incorporated porous SiO₂ xerogel low-k films. The SiO₂ xerogel thin films were prepared by sol–gel spin-on method using tetraethylorthosilicate as a source of Si. The hydrofluoric acid was used as a catalyst for the incorporation of F ion in the film matrix. The thickness and refractive index (RI) of the films were observed to be decreasing with increase in annealing temperature with minimum value 156 nm and 1.31 respectively for film annealed at 400 °C. Based on measured RI value, the 34 % porosity and 1.53 gm/cm³ density of the film annealed at 400 °C have been determined. The roughness of the films as a function of annealing temperature measured through AFM was found to be increased from 0.9 to 1.95 nm. The Electrical properties such as dielectric constant and leakage current density were evaluated with capacitance–voltage (C–V) and leakage current density–voltage (J–V) measurements of fabricated Al/SiO₂ xerogel/P–Si metal–insulator-semiconductor (MIS) structure. Film annealed at 400 °C, was observed to be with the lowest dielectric constant value (k = 2) and with the lowest leakage current (3.4 × 10^?8 A/cm²) with high dielectric breakdown.     

Study of the effect of thermal annealing on high k hafnium oxide thin film structure and electrical properties of MOS and MIM devices

The effect of rapid thermal annealing on structural and electrical properties of high k HfO₂ thin films is investigated. The films were initially deposited at pre-optimized sputtering voltage of 0.8 kV and substrate bias of 80 V in order to get optimized results for oxide charges and leakage current as a MOS device. The film properties were investigated for optimum annealing temperature in oxygen and optimum rapid thermal annealing temperature in nitrogen respectively to get the best electrical results as a MOS device structure. The film thickness, composition and microstructure is studied by Laser Ellipsometry, XRD and AFM and the effect of thermal annealing is shown. The electrical I–V and C–V characteristics of the annealed dielectric film were investigated employing Al-HfO₂-Si MOS capacitor structure. The flat-band voltage (V _fb) and oxide-charge density (Q _ox) were extracted from the high-frequency C–V curve. Dielectric study were further carried out on HfO₂ thin films having metal–insulator–metal (MIM) configuration over a wide temperature (300–500 K) and frequency (100 Hz to 1 MHz) range.     

Effect of annealing temperature on electrical and nano-structural properties of sol–gel derived ZnO thin films

Zinc oxide (ZnO) thin films have been prepared on silicon substrates by sol–gel spin coating technique with spinning speed of 3,000 rpm. The films were annealed at different temperatures from 200 to 500 °C and found that ZnO films exhibit different nanostructures at different annealing temperatures. The X-ray diffraction (XRD) results showed that the ZnO films convert from amorphous to polycrystalline phase after annealing at 400 °C. The metal oxide semiconductor (MOS) capacitors were fabricated using ZnO films deposited on pre-cleaned silicon (100) substrates and electrical properties such as current versus voltage (I–V) and capacitance versus voltage (C–V) characteristics were studied. The electrical resistivity decreased with increasing annealing temperature. The oxide capacitance was measured at different annealing temperatures and different signal frequencies. The dielectric constant and the loss factor (tanδ) were increased with increase of annealing temperature.     

Effect of annealing temperature on ZnO:Al/p-Si heterojunctions

Al-doped, zinc oxide (ZnO:Al) films with a 1.2 at.% Al concentration were deposited on p-type silicon wafers using a sol-gel dip coating technique to produce a ZnO:Al/p-Si heterojunction. Following deposition and subsequent drying processes, the films were annealed in vacuum at five different temperatures between 550 and 900 °C for 1 h. The resistivity of the films decreased with increasing annealing temperature, and an annealing temperature of 700 °C provided controlled current flow through the ZnO:Al/p-Si heterojunction up to 20 V. The ZnO:Al film deposited on a p-type silicon wafer with 1.2 at.% Al concentration was concluded to have the potential for use in electronic devices as a diode after annealing at 700 °C.     

Effects of post-deposition annealing temperature and ambient on RF magnetron sputtered Sm<Subscript>2</Subscript>O<Subscript>3</Subscript> gate on n-type silicon substrate

Samarium oxide (Sm₂O₃) thin films with thicknesses in the range of 15–30 nm are deposited on n-type silicon (100) substrate via radio frequency magnetron sputtering. Effects of post-deposition annealing ambient [argon and forming gas (FG) (90% N₂ + 10% H₂)] and temperatures (500, 600, 700, and 800 °C) on the structural and electrical properties of deposited films are investigated and reported. X-ray diffraction revealed that all of the annealed samples possessed polycrystalline structure with C-type cubic phase. Atomic force microscope results indicated root-mean-square surface roughness of the oxide film being annealed in argon ambient are lower than that of FG annealed samples, but they are comparable at the annealing temperature of 700 °C (Argon—0.378 nm, FG—0.395 nm). High frequency capacitance–voltage measurements are carried out to determine effective oxide charge, dielectric constant and semiconductor-oxide interface trap density of the annealed oxide films. Sm₂O₃ thin films annealed in FG have smaller amount of effective oxide charge and semiconductor-oxide interface trap density than those oxide films annealed in argon. Current–voltage measurements are conducted to obtain barrier heights of the annealed oxide films during Fowler–Nordheim tunneling.     

Structural and morphological investigations on DC-magnetron-sputtered nickel films deposited on Si (100)

Pure nickel thin films were deposited on Si (100) substrates under different conditions of sputtering using direct current magnetron sputtering from a nickel metal target. The different deposition parameters employed for this study are target power, argon gas pressure, substrate temperature and substrate-bias voltage. The films exhibited high density of void boundaries with reduction in <111> texture deposited under high argon gas pressures. At argon gas pressure of 5 mTorr and target power of 300 W, Ni deposition rate was ~40 nm/min. In addition, coalescence of grains accompanied with increase in the film texture was observed at high DC power. Ni films undergo morphological transition from continuous, dense void boundaries to microstructure free from voids as the substrate-bias voltage was increased from −10 to −90 V. Furthermore, as the substrate temperature was increased, the films revealed strong <111> fiber texture accompanied with near-equiaxed grain structure. Ni films deposited at 770 K showed the layer-by-layer film formation which lead to dense, continuous microstructure with increase in the grain size.     

Effect of evaporated copper and aluminum on post-annealed SiOC(-H) films deposited using plasma-enhanced chemical vapor deposition

Low dielectric constant SiOC(-H) films were deposited on p-type Si(100) substrates by plasma-enhanced chemical vapor deposition (PECVD) using dimethyldimethoxysilane (DMDMOS, C₄H₁₂O₂Si) and oxygen gas as precursors. We studied the detailed electrical characterization of SiOC(-H)/p-Si(100) interfaces using different experimental parameters for using the multilevel interconnections in ultra large-scale integrated circuits (ULSI). To improve the SiOC(-H)/p-Si(100) interface, the wafer was cleaned using the RCA process and rinsed with deionized water. The deposited SiOC(-H) films were annealed at different temperatures ranging from 250 to 450 °C in a vacuum. The interface properties of the SiOC(-H)/p-Si(100) with Cu/SiOC(-H)/p-Si(100)/Al metal-insulator-semiconductor (MIS) structures were investigated by capacitance-voltage (C-V) measurement with a flat band shift by electric field stress. Trapped charge, fixed oxide charge, and the interface trap density of SiOC(-H) films were related to the dielectric breakdown and leakage current density at the SiOC(-H)/p-Si(100) interface. From these analyses, detailed electrical properties defining the interface states of the MIS structures were reported.     

Electrical properties of pulsed laser deposited Bi<Subscript>2</Subscript>Zn<Subscript>2/3</Subscript>Nb<Subscript>4/3</Subscript>O<Subscript>7</Subscript> thin films for high K gate dielectric application

Metal Insulator Semiconductor (MIS) capacitors with monoclinic bismuth zinc niobate pyrocholre having the composition Bi2Zn2_/3Nb_4/3O₇ (m-BZN) dielectric layer were fabricated and characterized. Capacitance voltage (C–V) and current voltage measurements were utilized to obtain the dielectric properties, leakage current density and interface quality. The results shows that the obtained m-BZN thin films presents a high dielectric constant in between 30 and 70, a good interface quality with silicon and a leakage current density of 10 μA/cm² for a field strength of 100 kV/cm which is acceptable for high performance logic circuits. The equilent oxide thickness for the films annealed at 200 °C was 10 nm. These results suggest that m-BZN thin films can be potentially integrated as gate dielectric materials in CMOS technology.     

Structural and electrical studies of Cd<Subscript>1−x</Subscript>Zn<Subscript>x</Subscript> Te thin film by vacuum evaporation technique

Cd_1−xZn_xTe (where x = 0.02, 0.04, 0.06, 0.08) thin film have been deposited on glass substrate at room temperature by thermal evaporation technique in a vacuum at 2 × 10⁻⁵ torr. The structural analysis of the films has been investigated using X-ray diffraction technique. The scanning electron microscopy has been employed to know the morphology behaviour of the thin films. The temperature dependence of DC electrical conductivity has been studied. In low temperature range the thermal activation energy corresponding to the grain boundary—limited conduction are found to be in the range of 38–48 μeV, but in the high temperature range the activation energy varies between 86 and 1.01 meV. The built in voltage, the width of the depletion region and the operating conduction mechanism have been determined from dark current voltage (I–V) and capacitor-voltage (C–V) characteristics of Cd_1−xZn_xTe thin films.     

Study of annealing effects in In-Sb bilayer thin films

The thin films of In-Sb having different thicknesses of antimony keeping constant thickness of indium was deposited by thermal evaporation method on ITO coated conducting glass substrates at room temperature and a pressure of 10⁻⁵ torr. The samples were annealed for 1 h at 433 K at a pressure of 10⁻⁵ torr. The optical transmission spectra of as deposited and annealed films have been carried out at room temperature. The variation in optical band gap with thickness was also observed. Rutherford back scattering and X-ray diffraction analysis confirms mixing of bilayer system. The transverse I-V characteristic shows mixing effect after annealing at 433 K for 1 h. This study confirms mixing of bilayer structure of semiconductor thin films.     

Optical and mechanical properties of diamond like carbon films deposited by microwave ECR plasma CVD

Diamond like carbon (DLC) films were deposited on Si (111) substrates by microwave electron cyclotron resonance (ECR) plasma chemical vapour deposition (CVD) process using plasma of argon and methane gases. During deposition, a d.c. self-bias was applied to the substrates by application of 13·56 MHz rf power. DLC films deposited at three different bias voltages (−60 V, −100 V and −150 V) were characterized by FTIR, Raman spectroscopy and spectroscopic ellipsometry to study the variation in the bonding and optical properties of the deposited coatings with process parameters. The mechanical properties such as hardness and elastic modulus were measured by load depth sensing indentation technique. The DLC film deposited at −100 V bias exhibit high hardness (∼ 19 GPa), high elastic modulus (∼ 160 GPa) and high refractive index (∼ 2·16–2·26) as compared to films deposited at −60 V and −150 V substrate bias. This study clearly shows the significance of substrate bias in controlling the optical and mechanical properties of DLC films.     

The electrical and interface properties of metal-ferroelectric (lanthanum substituted bismuth titanate: BLT)-insulator-semiconductor (MFIS) structures with various insulators

We have investigated metal-ferroelectric-insulator semiconductor (MFIS) structures with lanthanum substituted bismuth titanate (BLT) as a ferroelectric layer and lanthanum oxide (LO) or zirconium silicate (ZSO) as an insulating buffer layer between BLT and Si substrate. The morphology of BLT films deposited on LO or ZSO oxide was not changed due to the good thermal stability of LO and ZSO films. But an interface reaction between BLT and buffer layer started at high annealing temperature (750 °C), which was confirmed by transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS). The maximum memory window was 3.59 V at a sweep voltage of 7 V with the LO film annealed at 650 °C and a thickness of 5 nm. With BLT/LO annealed at 750 °C, the window was decreased due to the reaction between the BLT film and LO. The memory window was about 1 V lower with a ZSO film because ZSO film has a lower dielectric constant than LO film. The MFIS structure annealed at 750 °C had a lower leakage current density because the electrical properties of the buffer layer (La oxide or Zr silicate) were improved by the thermal process.     

Frequency and gate voltage effects on the dielectric properties and electrical conductivity of Al∕SiO(2)∕p-Si metal-insulator-semiconductor Schottky diodes

The dielectric properties and electrical conductivity of Al∕SiO(2)∕p-Si (MIS) Schottky diodes (SDs) in the frequency range of 10 kHz to 10 MHz and the gate voltage range of -2 to 6 V have been investigated in detail using experimental C-V and G∕w-V measurements. Experimental results indicated that the voltage dependence of the real part of the dielectric constant (?') and loss tangent (tan δ) characteristics have a peak at each frequency. The values of ?' increase with decreasing frequency and tend to be frequency independent in the negative voltage region. However, the values of the dielectric loss (?″) increase with decreasing frequency at each voltage. In contrast, ?' and ?″ are almost found to decrease, and the ac electrical conductivity (σ(ac)) and the real part of the electric modulus (M') increase, with increasing frequency. In addition, the imaginary part of the electric modulus (M″) showed a peak that shifts to a higher frequency with increasing applied voltage. It can be concluded that interfacial polarization can more easily occur at low frequencies, and consequently the majority of interface states at the Si-SiO(2) interface contribute to the deviation of the dielectric properties of Al∕SiO(2)∕p-Si (MIS) SDs.     

以Ni-Al为底电极的P(VDF-TrFE)铁电电容器的结构与性能

应用磁控溅射法制备Ni-Al和Pt薄膜,溶胶-凝胶法制备P(VDF-TrFE)铁电共聚物薄膜,在SiO2/Si(001)衬底上首次构架了Pt/P(VDF-TrFE)/Ni-Al异质结电容器。X射线衍射(XRD)结果表明:Ni-Al薄膜为非晶结构,P(VDF-TrFE)薄膜具有较好的结晶质量。研究发现,在20 Hz测试频率下,Pt/P(VDF-TrFE)/Ni-Al电容器具有饱和的电滞回线,在90 V驱动电压下,剩余极化强度与矫顽场分别为7.6μC/cm2和45.7 V。在外加电压为40 V时,薄膜的漏电流密度约为5.37×10-6 A/cm2。漏电机制研究表明,Pt/P(VDF-TrFE)/Ni-Al电容器满足欧姆导电机制。铁电电容器经过109极化反转后没有发现明显的疲劳现象。     

Experimental and modeling study of the capacitance-voltage characteristics of metal-insulator-semiconductor capacitor based on pentacene/parylene

The capacitance-voltage (C-V) characteristics of metal-insulator-semiconductor (MIS) capacitors consisting of pentacene as an organic semiconductor and parylene as the dielectric have been investigated by experimental, analytical, and numerical analysis. The device simulation was performed using two-dimensional drift-diffusion methods taking into account the Poole-Frenkel field-dependent mobility. Pentacene bulk defect states and fixed charge density at the semiconductor/insulator interface were incorporated into the simulation. The analysis examined pentacene/parylene interface characteristics for various parylene thicknesses. For each thickness, the corresponding flat band voltage extracted from the C-V plot of the MIS structure was more negative than − 2.4 V. From the flat band voltage the existence of a significant mismatch between the work functions of the gate electrode and pentacene active material has been identified. Experimental and simulation results suggest the existence of interface charge density on the order of 3 × 10¹¹ q/cm² at the insulator/semiconductor interface. The frequency dispersion characteristics of the device are also presented and discussed.