A cascade energy band structure enhances the carrier energy in organic vertical-type triodes

Organic vertical-type triodes (OVTs) based on the cascade energy band structure as emitter layer are studied. The electric characteristics were dramatically enhanced while incorporating the cascade energy under current driving and voltage driving modes. The improvement is attributed to that injection carriers can obtain higher energy through a stepwise energy level. When the device has a layered structure of F₁₆CuPC (10 nm)/PTCDI (10 nm)/pentacene (100 nm) in emitter, it exhibits a common-base transport factor of 0.99 and a common-emitter current gain of 225 under current driving mode and exhibits a high current modulation-exceeding ?520 μA for a low collector voltage of ?5 V and a base voltage of ?5 V and the current on/off ratio of 10³ under voltage driving mode. Furthermore, we realized first organic current mirror that exhibited out/in current ratio of 0.75 and output resistance of 10⁵ Ω by using the OVTs.     

Cord identification technique for ultra-low bending loss fibers using higher order modes of visible light

We propose a cord identification technique for ultra-low bending loss fiber using higher order modes of visible light. With this kind of fiber, bending losses are greatly reduced and it is difficult to obtain sufficient leaked light with a conventional macro-bending technique. The bending loss of higher order modes is several orders larger than that of fundamental modes. Higher order modes can exist at shorter wavelengths and their guiding loss is small when the fiber is not tightly bent. As a result, higher order modes are suitable for cord identification purposes with ultra-low bending loss fiber. We determined that the LP₂₁ and LP₀₂ modes at 650 nm (red) and the LP₃₁ mode at 532 nm (green) are the most effective for cord identification purposes. We employed an offset launch technique to excite higher order modes, and achieved a sensitivity improvement of more than 14 dB. By using our method, a cord can be identified by red or green light even with the naked eye.     

Memory characteristics of Al2O3/La2O3/Al2O3 multi-layer films with various blocking and tunnel oxide thicknesses

In order to investigate charge trap characteristics with various thicknesses of blocking and tunnel oxide for application to non-volatile memory devices, we fabricated 5 and 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ and 15 nm Al₂O₃/5 nm La₂O₃/5, 7.5, and 10 nm Al₂O₃ multi-stack films, respectively. The optimized structure was 15 nm Al₂O₃ blocking oxide/5 nm La₂O₃ trap layer/5 nm Al₂O₃ tunnel oxide film. The maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in program mode and at ?13 V for 100 ms in erase mode. At these program/erase conditions, the threshold voltage of the 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ film did not change for up to about 10⁴ cycles. Although the value of the memory window in this structure was not large, it is thought that a memory window of 1.12 V is acceptable in the flash memory devices due to a recently improved sense amplifier.     

Investigation of voltage reduction in nanostructure-embedded organic light-emitting diodes

We investigated the reduction of the operating voltage in organic light-emitting diodes containing WO₃ nanoislands. The thickness of the organic layer and the periodicity of the nanoislands were varied in order to quantitatively analyze the electrical changes. The thickness of the N,N′-bis(naphthalen-1-yl)-N,N′-bis(phenyl)-benzidine (NPB) layer was varied from 150 nm to 600 nm, and various periodic nanoislands of 300 nm, 330 nm, and 370 nm were fabricated. Two geometric factors, which are the effective length and effective area, influence the operating voltage. The effective length is determined by the relative thickness of the nanoislands compared with the organic thickness, and the reduction of the operating voltage is linearly proportional to the relative thickness. The effective area is a nonlinear function of periodicity, and the voltage is reduced as the periodicity decreases.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback

This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130 nm and 90 nm. In both cases, the supply voltage is 1.2 V. The best LNA designed in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A_v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology designed in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are input-impedance matched and have a noise figure below 2.4 dB measured at 2.4 GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130 nm technology, achieving an area of 0.012 mm², which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.¹     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Trapping of hyaluronic acid molecules on sharp nano-electrodes of various metals

This paper reports on the trapping of hyaluronic acid (HA) molecule from an aqueous solution by using a pair of sharp thin film nano-electrodes with a gap of 3 μm on an SiO₂ surface which is hydrophobic due to hexamethyl-disilazane (HMDS) treatment. By applying high frequency AC voltage with a sine wave, the HA molecule (about 10 μm long) can be trapped between the Al nano-electrode tips. A frequency of 500 kHz or higher and peak-to-peak voltage of 20 V or higher were necessary to trap the HA molecular string. The width and height of the trapped HA molecule were 45–60 nm and 5–10 nm, respectively, indicating that the trapped string was a bundle of molecules. In addition to the Al electrode, HA molecules can be trapped to both Au and Pt electrodes subject to HMDS post-treatment to ensure the substrate surface is sufficiently hydrophobic. The results suggest that the trapping of the HA molecule is caused not by a chemical reaction with the metal surface but by physical adhesion to the metal surface.     

Effect of periodically modified n-type electron transport layers on the optoelectrical performance of organic light-emitting diodes

We have investigated the characteristics of Cs₂CO₃ doped 4, 7-Diphenyl-1, 10-phenanthroline (Bphen) film and the effects of its thickness on the optoelectrical performance of microcavity organic light-emitting diodes. By doping Cs₂CO₃ into Bphen, higher current density and lower turn-on voltage could be achieved with barely changing the external quantum efficiency. Three types of resonators were fabricated by varying the thickness of every a quarter of electron transport layers, i.e. 152.5 nm (0.25 λ), 305 nm (0.5 λ), and 610 nm (1.0 λ). The 0.25λ-based microcavity organic light-emitting diode was found to exhibit the lowest waveguided loss coefficient of 118.0 cm⁻¹, while the relative emission intensity of edge mode to surface reached about 2118.8 times, indicating that this mode underwent a very low attenuation during its propagation.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Ultra-long Si3N4 nanobelts prepared by nanosilicon,nanosilica and graphite

The composition and morphology of obtained products depended on the processing atmosphere using the raw materials of nanosilicon, nanosilica and graphite, with N₂-generating several millimeters long single-crystal Si₃N₄ nanobelts (NBs) and Ar SiC nanobelts. The width and thickness of in situ NBs ranged from 100 to 300 nm and 50–100 nm with an average width of 196 nm, while the width and thickness of ex situ NBs fluctuated from 150 to 500 nm and 80–200 nm with an average width of 436 nm. Alumina-assisted VS mechanism was proposed for the growth mode of in situ growth of Si₃N₄ nanobelts, while a combined mechanism involving VS and VLS was controlled the growth of Si₃N₄ nanobelts obtained on the inner walls of the crucible due to the presence of Fe₂O₃, which provides an effective means of fabricating ultra-long Si₃N₄ nanobelts on an industrial scale.     

Short-channel effect and device design of extremely scaled tunnel field-effect transistors

For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of tunnel-field effect transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5 × 10¹⁷ cm⁻³ and a minimum length of 20 nm enables 5 nm TFETs to exhibit favorable on–off switching characteristics. In sub-20 nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25 nm to sustain reversely biased drain voltage of 0.7 V. The asymmetric Si_1−xGe_x source heterojunction is combined with the minimum drain design in 5 nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5 nm TFETs.     

Active layer thickness effect on the recombination process of PCDTBT:PC71BM organic solar cells

We investigated the effect of active layer thickness on recombination kinetics of poly[N-9″-hepta-decanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)] (PCDTBT) and [6,6]-phenyl C71-butyric acid methyl ester (PC₇₁BM) based solar cells. Analysis of the fitted Lambert W-function of illuminated current density–voltage (J–V) characteristics revealed increased recombination processes with increased active layer thicknesses. The ideality factor extracted from PCDTBT:PCBM solar cells continuously increased from 1.89 to 3.88 when photoactive layer thickness was increased from 70 to 150 nm. We found that such increase in ideality factor is closely related to the defect density which is increased with increased photoactive layer thickness beyond 110 nm. Therefore, the different density of defect states in PCDTBT:PCBM solar cells causes the different recombination paths where solar cells with a thicker active layer (?110 nm) are considered to undergo coupled trap-assisted recombination processes while single-defect trap-assisted recombination is dominant for thinner (70–90 nm) PCDTBT:PCBM solar cells. As a result, we found that the optimal efficiencies of PCDTBT:PC₇₁BM solar cells were limited to the active layers between 70 and 90 nm. Particularly, when PCDTBT:PC₇₁BM solar cells were optimized with an active layer thickness of 70 nm, energy conversion efficiency reached 6.5% while an increase in thickness led to the reduction of efficiency to 4.7% at 133 nm but then an increase to 5.02% at 150 nm.     

A new method to simulate random dopant induced threshold voltage fluctuations in sub-50 nm MOSFET’s with non-uniform channel doping

In this paper, based on a precise and efficient analytical function of relatively realistic dopant fluctuations, a new method is proposed to simulate the threshold voltage variation of MOSFET’s with non-uniform channel doping due to random dopant fluctuations. Both the number and position fluctuations of dopants are taken into account. Using this method, 2500 microscopically different devices under certain process conditions that cover the range of channel length L from 35 nm to 90 nm, oxide thickness T_ox from 1 nm to 4 nm and channel surface doping concentration N_A from 1 × 10¹⁸ to 5 × 10¹⁸ cm⁻³ are simulated to show how our method works.     

Multiple defect core photonic crystal fiber with high birefringence induced by squeezed lattice with elliptical holes in soft glass

We present a dual mode, large core highly birefringent photonic crystal fiber with a photonic cladding composed of elliptical holes ordered in a rectangular lattice. The fiber is made of borosilicate glass and has a regular set of elliptical holes with an aspect ratio of 1.27 and a filling factor near 0.5. The group birefringence (G) and effective mode area were measured at 1550 nm for the fundamental mode and were found to equal 2 × 10^?4 and 20 μm² respectively. We discuss the influence of structural parameters including the ellipticity of the air holes and the aspect ratio of the rectangular lattice on the birefringence and on the fundamental and second modes of the fiber.     

Potentiality of healing techniques in hot-carrier damaged 28 nm FDSOI CMOS nodes

We have developed the possibility of using healing phases on hot-carrier (HC) degraded transistors from devices to logic cells (1) by the combined effects of oxide charge neutralization and channel shortening (2) using back bias V_B sensing effects in forward (FBB) mode in 28 nm FDSOI CMOS node. This is done for DC to AC operations from Input-Output device (EOT = 3.6 nm) to core blocks (EOT = 1.35 nm) leading to an almost complete cure of HC damaged devices for digital application. Continuous or short sequences of healing phases help to regenerate HC degraded parameters (I_On, V_T) offering new perspectives for on time repeatedly cure digital operation as well as under some analog case.     

Characteristics of InAIAs/InP and InAIP/GaAs native oxides

Characteristics of InAlAs/InP and InAlP/GaAs wet oxidation layers were measured for the first time. These oxidation layers can be a current blocking or an optical confining layer in laser diodes. These layers were well made at 500–575 °C. The oxidation rates at 525 °C are approximately 340 nm/h and 120 nm/h for InAlAs and InAlP oxides, respectively. The refractive index are 1.82–1.90 for InAlAs oxide and 1.565–1.595 for InAlP oxide between 0.6 μm and 1.65 μm wavelength. The characteristics are not much varied with processing temperatures except the oxidation rate. And a 200 nm thick InAlAs oxidation layer has a current–voltage characteristic that currents rapidly flow at about 10 V, which is much lower than that of SiO₂.     

Phonon–plasmon coupling in Si doped GaN nanowires

The vibrational properties of silicon doped GaN nanowires with diameters comprised between 40 and 100 nm are studied by Raman spectroscopy through excitation with two different wavelengths: 532 and 405 nm. Excitation at 532 nm does not allow the observation of the coupled phonon–plasmon upper mode for the intentionally doped samples. Yet, excitation at 405 nm results in the appearance of a narrow peak at frequencies close to that of the uncoupled A₁(LO) mode for all samples. This behavior points to phonon–plasmon scattering mediated by large phonon wave-vector in these thin and highly doped nanowires.     

A flexible moisture barrier comprised of a SiO2-embedded organic–inorganic hybrid nanocomposite and Al2O3 for thin-film encapsulation of OLEDs

We demonstrated a high performance flexible multi-barrier containing a silica nanoparticle-embedded organic–inorganic hybrid (S–H) nanocomposite and Al₂O₃. The multi-barrier was prepared by low-temperature Al₂O₃ atomic layer deposition and with a spin-coated S–H nanocomposite. The moisture barrier properties were investigated with a water vapor transmission rate (WVTR), estimated by a Ca test at 30 °C, 90% R.H.. Moisture diffusion was effectively suppressed by the sub-700 nm thick multi-barrier incorporating well-dispersed silica nanoparticles in the organic layer. A low WVTR of 1.14 × 10^?5 g/m² day and average transmittance of 85.8% in the visible region were obtained for the multi-barrier. After bending under tensile stress mode, the moisture barrier property of the multi-barriers was retained. The multi-barrier was successfully applied to thin-film encapsulation of OLEDs. The thin-film encapsulated OLEDs showed practicable current–voltage–luminance (I–V–L) characteristics and stable real operation over 700 h under ambient conditions.