A methodology for analysis of RTCVD systems

A methodology for predicting the spatial and temporal distribution of film thickness is given for low pressure chemical vapor deposition (LPCVD) in rapid thermal processor (RTP) systems. The methodology is based on a model for the heat transfer to, from, and within the wafer, a geometric ray trace algorithm to predict the radiant heat transfer from the lamps and reflectors to the wafer, a deposition model for the deposited film thickness, and an optical properties model that gives the wafer absorptivity and emissivity. The modeling is for low pressure processes, where gas flow effects are secondary, and concentrates on the radiant heat transfer to and from the wafer. The methodology is based on physical principles, with a minimum reliance on empirical and experimental data, and has been validated by comparison with deposited films from a cylindrical RTP system     

Validation of a Rapid Thermal Processing model in steady-state

Rapid Thermal Processing (RTP) is widely used in advanced semiconductor manufacturing. The present work deals with the heat transfer from infrared lamps to the silicon wafer in a commercial RTP equipment. Both numerical and experimental approaches are considered. For numerical purposes, the RTP system is modelled in two (2D) and three dimensions (3D). Calculations are performed in steady-state. The computational fluid dynamics method (CFD) is used for solving the mass and heat conservation equations. The radiative heat transfer equation is solved with the Monte Carlo method. In order to validate these models, measurements of the wafer temperature are realized for five electric power values supplied to the infrared lamps. The experimental wafer temperature profiles are in good agreement with the numerically calculated ones. Moreover, a confrontation between the experimental temperature of the infrared lamp filaments evaluated from the Ohm law and the one used in the numerical calculations shows a good agreement with the 3D model. The slight difference observed with the 2D model is explained. So the numerical simulations are fully validated. Two relations are established in order to predict the power which has to be applied to infrared lamps to obtain the required wafer temperature.     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Using wavelength-dependent emissivity of semiconductor wafer tomodel heat transfer in rapid thermal processing station

This paper develops an approach for using a wavelength-dependent emissivity model of a semiconductor wafer in calculating heat transfer in a rapid thermal processing (RTP) station. The wafer emissivity is modeled by a generalized polynomial in wavelength where the coefficients may be functions of temperature. A comparison of experimental data with simulated results for a silicon wafer is provided     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

In situ measurement of wafer temperatures in a low pressurechemical vapor deposition furnace

Axial and radial temperature profiles within the wafer load of a multiwafer LPCVD furnace were measured in situ using a pair of instrumented wafers. The measurements confirm that the wafer load is not in thermal equilibrium with the furnace tube, as has been widely assumed in many modeling studies. The measurements confirm temperature variations predicted previously from a study of polysilicon film thickness profiles. Temperature variations were small for wafers near the center of the 150-wafer load. However, axial variations of up to 25°C and radial variations of up to 5°C were measured at the extremes of the wafer load. For a representative polysilicon deposition data set, axial and radial thin-film thickness variations were found to correlate closely with measured temperature variations. The temperature profile was found to be insensitive to gas composition and flowrate, establishing radiation as the dominant mode of heat transfer. A pair of polysilicon coated quartz radiation shields was shown to improve polysilicon film thickness uniformity both down the load (along the furnace axis) and across each wafer     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed     

Modeling of three-dimensional effects on temperature uniformity inrapid thermal processing of eight inch wafers

A three-dimensional steady-state model of the industry-standard AG Associates 4108 Heatpulse Rapid Thermal Processing system has been developed for the study of thermal uniformity across 8 inch wafers. The model combines radiation energy transfer among all solid surfaces in the chamber with energy transfer among the chamber materials and to the process ambient. Surfaces included are those of the tungsten filaments of the lamps, the silicon wafer, the polysilicon annular thermal guard ring, the quartz process tube, and the gold reflectors which surround the lamps and process tube. These surfaces are divided into approximately 4800 individual surface elements for the radiation transfer allowing very accurate thermal analysis. The model has previously been shown to provide very good agreement with experiment for temperature distributions across an 8 inch wafer. The model is presently used to make quantitative examinations of asymmetric effects occurring in a RTP chamber which cannot be examined by 2-dimensional models. Situations examined include the effect of nonuniform lamp power distributions. Also examined is tilting of the wafer with respect to the flow tube and reflective chamber     

Effect of radiation shield angle on temperature and stress profilesduring rapid thermal annealing

The effects of radiation shield angle and oven-temperature ramping rates on the temperature and thermal stress profiles in a gallium arsenide wafer undergoing rapid thermal annealing are studied. The numerical model of the heat transfer in a cylindrical oven considers conduction in the wafer radiative heat transfer from all oven and shield surfaces to the wafer. All simulations show that at some location in the wafer the induced thermal stress exceeds the critical stress. These results indicate that at high temperatures (T>750°C) it is very difficult to maintain a sufficiently flat temperature profile such that the induced thermal stress is maintained below the critical stress throughout the wafer. Possible ways to minimize the induced thermal stress during the annealing process using a radiation shield and specific oven-temperature ramping rates are discussed     

Investigation of the thermal behavior of a RTP furnace

The results of a full model accounting for the thermal behavior of a commercially available rapid thermal processing furnace are given. In particular, emphasis has been placed on achieving a flat temperature profile over the wafer. System parameters allowing RTP equipment to be improved are reviewed     

Model-based emissivity correction in pyrometer temperature controlof rapid thermal processing systems

Single-wavelength pyrometers are most often used to infer wafer temperature in rapid-thermal-processing (RTP) systems. A constant wafer emissivity is assumed with a pyrometer, but a variation in the wafer's surface emissivity can result in an error in the inferred temperature which affects the temperature control of the RTP system. A time-dependent variation is evident in rapid thermal chemical vapor deposition where the emissivity is a function of the film type and thickness. An approach which uses a physically based model of the emissivity variation as part of the feedback control loop is described. The technique employs a first-order model of the emissivity as a function of film thickness from which a projected actual wafer temperature is inferred. The film thickness is approximated using a valid growth-rate expression and temperature as a function of time. These models are then incorporated into the feedback loop of the RTP control system     

Temperature distribution in semiconductor wafers heated in ahot-wall-type rapid diffusion furnace

Transient temperature distribution was calculated for wafers heated in a new hot-wall-type rapid diffusion furnace. Two-dimensional radiative heat transfer was combined with unsteady conduction in wafers and the furnace. The furnace is composed of parallel plate heaters, and heats wafers to a temperature of about 1000°C. The heaters are divided into four zones and their heating powers are PID-controlled. Two wafers on a holder are inserted vertically from the bottom of the furnace, and heated for three minutes. The calculated results show the wafer temperature approached the desired heating temperature about one minute after insertion, agreeing with experimental results. The average temperature distribution in the wafers during heating is found to be within ±1°C at 1000°C, when the heating power (temperature) of the four zones is properly controlled. The effects of heater temperature, insertion speed, and holder thickness on the temperature distribution in wafers were calculated. The new hot-wall-type rapid diffusion furnace can be used to manufacture future VLSI     

The effect of patterned susceptor on the thickness uniformity ofrapid thermal oxides

A temperature compensation concept suitable for rapid thermal processing (RTP) with a nonuniform wafer temperature distribution is proposed in this work. Concentric Si rings with different diameters are placed on planar quartz or Si susceptors and are regarded as patterned susceptors for temperature compensation. We put monitor wafers on the patterned susceptor and see the effect of the patterned susceptor on the oxide thickness uniformity of the monitor wafers. The Si rings work as radiation barriers when placed on the quartz susceptor, but as heat conduction media when placed on the Si susceptor. By properly arranging the Si rings on the planar susceptors, the monitor wafers' oxide thickness uniformity can be improved     

A global model for rapid thermal processors

A simple model for the components that make up a rapid thermal processing system is given. These components are the furnace, the pyrometer used to measure temperature, and the control system that utilizes the pyrometer measurement to control the power to the lamps. The models for each of the components are integrated in a numerical code to give a computer simulation of the complete furnace operation. The simulation can be used to investigate the interaction of the furnace, temperature-sensing technique, and the control system. Therefore, the interplay of heat transfer (furnace) properties, optical (pyrometer) parameters, and control gains can be studied. The objective is to define variability in wafer temperature as process parameters change. The following three applications of the model are included: (1) a simulation of open-loop operation; (2) a simulation of the ramp up and subsequent operation with a step change in wafer optical properties; and (3) a simulation of the rapid thermal chemical vapor deposition of polysilicon on silicon oxide which demonstrates the applicability model for actual processes. A technique for correction of pyrometer output to improve temperature control is also presented     

Prediction of defect onset conditions in heat cycling based on athermoelastic wafer model

A thermoelastic wafer model is proposed for predicting defect onset conditions during heat cycling in a furnace. This model is formulated for application to the plane stress state under thermal loading. The wafer temperature is calculated by a wafer temperature model proposed in a previous work. Predictions are tested by comparison with the thermal stresses resolved on the slip systems of the silicon crystal under the process conditions (i.e. furnace temperature, insertion velocity, and wafer spacing). When the proposed model is applied to 125-mm diameter and 150-mm-diameter wafers, it is shown that the thermal stress level is reduced to about a half by increasing the wafer spacing by a factor of two or three. Accordingly, the predicted defect onset results based on this model are in reasonable agreement with experiments     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

Semi-Empirical Model-Based Multivariable Iterative Learning Control of an RTP System

Comprehensive study on control system design for a rapid thermal processing (RTP) equipment has been conducted with the purpose to obtain maximum temperature uniformity across the wafer surface, while precisely tracking a given reference trajectory. The study covers from model development, identification, optimum multivariable iterative learning control (ILC), to reduced-order controller design. The highlight of the study is the ILC technique on the basis of a semi-empirical dynamic radiation model named as$T^4$-model. It was shown that the$T^4$-model-based ILC technique can remarkably improve the performance of RTP control compared with the ordinary linear model-based ILC. In addition, reduced-order control methods and the associated optimum sensor location have been addressed. The proposed techniques have been evaluated in an RTP equipment fabricating 8-in wafers.     

Design and modeling of rapid thermal processing systems

The concept of rapid thermal processing (RTP) has many potential applications in microelectronics manufacturing, but the details of chamber design, temperature dynamics, process control, and temperature measurement remain active areas of research. This paper discusses the design rules used in an RTP test bed installed at SEMATECH with respect to the placement of lamps and the geometry and reflectivity of the enclosure. The distribution of light across the wafer was modeled, and a theory fur the wafer's dynamic temperature response was derived analytically with a few simplifying assumptions, parameters for this model were estimated from experimental data to yield a set of linear ordinary differential equations with temperature dependent coefficients. This particular model form is convenient for control system design and analysis     

Control of MMST RTP: repeatability, uniformity, and integration forflexible manufacturing [ICs]

A real-time multivariable strategy is used to control the uniformity and repeatability of wafer temperature in rapid thermal processing (RTP) semiconductor device manufacturing equipment. This strategy is based on a physical model of the process where the model parameters are estimated using an experimental design procedure. The internal model control (IMC) law design methodology is used to automatically compute the lamp powers to a multizone array of concentric heating zones to achieve wafer temperature uniformity. Control actions are made in response to real-time feedback information provided by temperature sensing, via pyrometry, at multiple points across the wafer. Several modules, including model-scheduling and antiovershoot, are coordinated with IMC to achieve temperature control specifications. The control strategy, originally developed for prototype equipment at Stanford University, is analyzed via the customization, integration, and performance on eight RTP reactors at Texas Instruments conducting thirteen different thermal fabrication operations of two sub-half-micron CMOS process technologies used in the the Microelectronics Manufacturing Science and Technology (MMST) program