Wafer-level chip size package (WL-CSP)

Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost     

圆片级封装技术展望

圆片级封装(Wafer-Level Packa-ging,WLP)已成为先进封装技术的重要部分。全圆片级封装虽然能够为芯片封装带来批量加工的规模经济效益,但由于系统集成方面的某些因素限制了其在主流应用中的推广。在圆片规模上开始加工,但结束于芯片规模的部分圆片级封装将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。     

技术评价:圆片级封装

本文对圆片级封装的定义、演变、进展状况及支撑技术进行了介绍和分析评论。     

圆片级封装技术及其应用

本文介绍了圆片级封装的设计考虑、基础技术、可靠性、应用情况及发展趋势。     

基于BCB键合的MEMS加速度计圆片级封装工艺

对基于BCB的圆片级封装工艺进行了研究,该工艺代表了MEMS加速度计传感器封装的发展趋势,是MEMS加速度计产业化的关键。选用3000系列BCB材料进行MENS传感器的粘结键合工艺试验,解决了圆片级封装问题,在低温250℃和适当压力辅助下≤2．5bar（1bar=100kPa）实现了加速度计的圆片级封装,并对相关的旋涂、键合、气氛、压力等诸多工艺参数进行了优化。     

现代圆片级封装技术的发展与应用

本文论述了圆片级封装的发展、优势、种类、应用、研究课题及产业化注意事项。     

Wafer-level LED-SiP based mobile flash module and characterization

In this paper, we have developed and revealed the wafer-level LED system-in-packaging (WL-LED-SiP) design and process platform. This platform provided an LED system solution with high packaging density, high performance, high reliability and cost effectiveness. Camera phone flash module was adopted as a test vehicle for demonstrating LED-SiP platform technologies, including wafer-level (WL) process integration with micro electromechanical system (MEMS) reflector, cavity-based lithography and through silicon via (TSV) filling. Meanwhile, LED flash module performance, including correlated color temperature (CCT), color rendering index (CRI), light energy and distribution, was characterized. The delivered LED-SiP flash module showed wide-view angle design of 80° × 50° and light energy of 5.7 lx s @ 1/30 s. The volume of the module is 8 × 11 × 4 mm³.     

Wafer-level bonding/stacking technology for 3D integration

Enhanced transmission speeds, lower power consumption, better performance, and smaller form factors are reported as advantages in many devices and applications when using 3D integration. One core technique for performing 3D interconnection is stacked bonding. In this paper, wafer-level bonding technologies are reviewed and described in detail, including bonding materials and bonding conditions. The corresponding 3D integration technologies and platforms developed world-wide are also organized and addressed.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Pulsed wave interconnect

Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wave-packets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-/spl mu/m CMOS technology case study, SPICE simulations show that pulsed wave interconnect can save up to 50% of energy and /spl sim/30% of chip area in comparison with the repeater insertion method. A proposed signal splitting structure provides reasonable isolations between different receivers. Measured S-parameters of 3.8-mm interconnect lines fabricated through CMOS foundry showed that the distortion and attenuation of a pico second signal are much less serious than the theoretical predictions. Pulsed wave interconnect also enables time division application of a single line to boost its bit rate capacity. The use of nonlinear transmission lines (NLTL) is also proposed to overcome pulse broadening and attenuation caused by dispersion and frequency-dependent losses. Pulsed waves on an NLTL may be generated, transmitted, split and detected with components realizable in bulk and SOI CMOS technologies. Tapered NLTL can be used for pulse compression. NLTL edge sharpening abilities may be applicable for signal rise time control.     

大规模晶圆级焊球置放关键的成功因素

芯片规模封装是对焊球置放至晶圆、条和基板上有更快增长需求的技术之一。明确合适工艺所需的关键成功因素可以使我们确立一整套最佳的工作方法,并保证能达到生产能力、产量和置放焊球成本方面的目标。     

Wave-breaking on CMOS interconnect

Nonlinear transmission lines exhibit negative dispersion that can give rise to wave-breaking and pulse shaping behaviour that is of practical use in high-speed electronics. Here, a silicon interconnect design incorporating a high degree of nonlinearity that is capable of producing wave-breaking, is demonstrated. Such nonlinear interconnect could be valuable in distributing ultrafast clock signals across lossy silicon substrates     

Wafer-level chip scale packaging: benefits for integrated passivedevices

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost     

基于SiC MOSFET的霍尔迁移率在片测试方法

研究了一种霍尔迁移率在片测试方法,通过在片测量反型层电荷密度ns和反型层方块电阻Rs得到反型层载流子的霍尔迁移率。通过在待测芯片上固定一个环形磁体获得一个高强度磁场,并且测试磁体与芯片距离和磁场强度的关系。讨论了反型层电荷密度ns和反型层方块电阻Rs的测试原理和方法,采用多次测量求导的办法,消除了霍尔电压测试过程中由于样品制备和测试系统的原因引入漂移电压,提高了测试精度。基于该方法完成测试平台搭建,并应用该测试平台完成了对SiC MOSFET样品霍尔迁移率的测试,得到了霍尔迁移率随栅极电压变化的关系。     

Well-behaved global on-chip interconnect

Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-/spl mu/m-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-/spl mu/m process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.     

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.     

Power characteristics of inductive interconnect

The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.     

Multi-objective optimization of interconnect geometry

The rapid increase in the number of wiring layers due to improved planarization and metallization techniques permits spatial resources to be traded for improved performance. Yield, power dissipation and propagation delay are all sensitive to the selection of the pitch and width of wires in each layer. As in many other engineering design problems, however, there exists no unique solution which simultaneously optimizes all aspects of system performance. The best that can be achieved is the identification of the optimal surface within the multi-objective performance space. A single design can be chosen from this list a posteriori using additional selection criteria which may depend, for example, on the specific details of the product application. This paper investigates the use of Pareto genetic algorithms to explore the extent of multi-objective optimal surfaces. The tradeoffs between yield, power-dissipation and cycle time for a benchmark netlist are examined as a function of in-plane geometry for a seven-layer interconnect.     

Circuit sensitivity to interconnect variation

Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations