Lifetime prediction of electrical connectors under multiple environment stresses of temperature and particulate contamination

Electrical connectors play a significant role in the electronic and communication systems. As they are often exposed in the atmosphere environment, it is extremely easy for them to cause electrical contact failure. It is essential to carry out the reliability modeling and predict the lifetime. In the present work, the accelerated lifetime testing method which is on account of the uniform design method was designed to obtain the degradation data under multiple environmental stresses of temperature and particulate contamination for electrical connectors. Based on the degradation data, the pseudo life can be acquired. Then the reliability model was established by analyzing the pseudo life. Accordingly, the reliability function and reliable lifetime function were set up, and the reliable lifetime of the connectors under the multiple environment stresses of temperature and particulate contamination could be predicted for electrical connectors.     

切换模拟或数字信号的开／关缓冲器

很多应用都需要使用在数字控制下切换模拟信号或数字信号的方法。这种开关的期望规格包括：当开关处于关断状态时,衰减小于90 dB；当开关处于打开状态时,失真不大于0.002%；以及能在10μs以内响应开、关命令的能力。另外,电路应     

Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses

The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this.     

Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses

We report on the reliability of InGaAs/InP DHBT technology which has applications in very high-speed ICs (over 100 Gbits/s). This work presents the results of accelerated aging tests under thermal and electrical stresses performed on HBT up to 2000 h. Stress conditions consist in applying collector–emitter bias V_CE from 1.3 to 2.7 V and collector current densities J_C of 400 and 610 kA/cm². The corresponding junction temperatures T_J extends from 83 to 137 °C. The base current ideality factor η_B increase and the current gain β decrease have revealed a degradation of the base–emitter junction. The normalized current gain β_norm drop has occurred earlier for higher V_CE and/or higher T_J. A 20% decrease of β_norm chosen as the failure criterion leads to an activation energy of 1.1 eV.     

Reversible dielectric breakdown in ultrathin Hf based high-k stacks under current-limited stresses

The effects of a current-limited breakdown (BD) on the post-BD current of MOS capacitors with a thin high-k dielectric stack have been analysed. A strong current reduction after BD and, consequently, a partial recovery of the insulating properties of the dielectric stack is observed. The similarities with the resistive switching phenomenon observed in MIM structures for memory applications are discussed.     

Defect generation in InGaN/GaN light-emitting diodes under forward and reverse electrical stresses

Electrical and optical degradations of GaN/InGaN single-quantum-well light-emitting diodes (LEDs) under high-injection current (150 A/cm²) and reverse-bias (−20 V) stresses were investigated. A substantial increase in the tunneling components of both forward and reverse currents was observed in the devices subjected to reverse biases. However, the stressed LEDs exhibited minimal degradation of optical characteristics. For devices subjected to high forward currents, a monotonic decrease in light intensities with stress time, accompanied by an increase of forward leakage current, was observed in the low-injection region, but a positive stress effect was found on the light output measured at high currents. These degradation behaviors can be explained by slow generation of point defects in the LEDs via different mechanisms, i.e., thermally induced defect formation in the InGaN active region in the devices subjected to high-injection currents, and destructive microstructual changes as a result of impact ionization in the cladding layer in the devices under high reverse-bias stress.     

Reliability prediction of imperfect switching systems subject to multiple stresses

Reliability prediction plays a very important role in system design, and the two key factors considered in predicting system reliability are: failure distribution of the component/equipment and system configuration. This paper discusses about the imperfect switching system with one component in active and k spares in the standby state. When the operating component breaks down, the switch will be able to detect the failure using the sensor and replace the defective component with a functionable spare, so the system can keep operating. Therefore, the switch and the sensor have direct impact on normal operations of the switching systems.The reliability of two types of imperfect switching system is thoroughly discussed and compared: (1) a non-repairable system with only one standby component, one switch and one sensor and (2) a non-repairable system with two standby components, one switch and one sensor. Since gamma distribution is fairly adequate to describe the failure mechanism of a system under k-times of shock multiple stresses. This paper then assumes in system (1) and (2), the operating components follow gamma failures, sensor and switch failures follow exponential distribution. In addition, three modes are assumed in regards to the switch failure: under energized, under failing-open and under failing-closed condition.This paper uses MAPLE computer language to perform reliability estimation and comparison on the above-mentioned systems with components, switch and sensor under different failure rate and various intended period of use. Its results can provide guidelines on decision making for improving system design in industries.     

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.     

Reliability study of underfill/chip interface under accelerated temperature cycling (ATC) loading

Interface reliability issue has become a major concern in developing flip chip assembly. The CTE mismatch between different material layers may induce severe interface delamination reliability problem. In this study, multifunctional micro-moiré interferometry (M³I) system was utilized to study the interfacial response of flip chip assembly under accelerated thermal cycling (ATC) in the temperature range of −40 °C to 125 °C. This in-situ measurement provided good interpretation of interfacial behavior of delaminated flip chip assembly. Finite element analysis (FEA) was carried out by introducing viscoelastic properties of underfill material. The simulation results were found to be in good agreement with the experimental results. Interfacial fracture mechanics was used to quantify interfacial fracture toughness and mode mixity of the underfill/chip interface under the ATC loading. It was found that the interfacial toughness is not only relative to CTE mismatch but also a function of stiffness mismatch between chip/underfill.     

Effect of HTRB lifetest on AlGaN/GaN HEMTs under different voltages and temperatures stresses

Space and transport industries are facing a strong global competition which is setting economic constraints on the entire supply chain. In order to address decreasing development costs and to propose new features, components-off-the-shelf (COTS) have become a very attractive solution. This paper investigates the degradation of AlGaN/GaN HEMTs COTS submitted to HTRB lifetest. Temperature and voltage step stresses were applied to untangle the effect of each stressor. The main aim is to establish a lifetime model, taking into account several degradation mechanisms, over a large range of temperatures and voltages. The experimental outcomes highlight the activation of different failure mechanisms occurring during the stress tests, and which depend from the different temperature and voltage working ranges. In this work, experimental analysis has been performed in order to characterize the root cause behind the activation of these multiple failure mechanisms and estimate the operative range where they may superimpose.     

Life prediction of HCPV under thermal cycling test condition

High-concentration photovoltaic (HCPV) module is subject to larger thermal stress due to its more severe temperature fluctuation in real operating conditions. In the thermal cycling test, excessive thermal stress might occur at the peripheral solder layer. For the large area bonding structure, thermal-induced stress is the main cause for cracks. Crack growth is expected to start from the edges of the solder layer and progress to the center. The shrinkage of the bonding area increases the junction temperature of solar cells and reduces the energy-conversion efficiency of the HCPV module. In this study, the stress/strain behavior of the HCPV module under thermal cycling test is analyzed using finite element analysis software, ANSYS®. Results indicate that the von Mises creep strain distribution at the solder layer’s edge is independent of the package’s dimensions. The lifetime of HCPV with uniform solder layer could be predicted by assuming that the crack propagation rate is constant during solder layer degradation. Furthermore, lifetime of tilted HCPV module could be predicted by compensating the variation of thickness of solder layer during crack propagation.     

On/off current ratio in P-channel poly-Si MOSFETs: dependence onhot-carrier stress conditions

Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V_GS=V_DS=-11 V, but can be increased by a factor of 50 for a stress bias of V_GS=-2 V, V_DS=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V_GS. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation     

面向能力培养的嵌入式课程体系建设探析

嵌入式课程融合了电子技术、计算机技术、网络技术等诸多专业的一门综合性课程,由于各项技术的不断发展,给嵌入式课程教学带来了新的挑战,基于课程教学现状,分析教学中存在的问题,提出了四个层面的嵌入式课程体系建设,对嵌入式课程知识体系进行详细设计,对课程理论知识体系及实践方案进行构建,提出了五个层面的嵌入式理论知识体系,以期提...     

Reliability analysis of UHF RFID tags under long-term mechanical cycling

Radio Frequency Identification is becoming more and more popular although unit price of RFID tags is still higher than price of barcodes. Further decrease in cost of using RFID techniques can be possible to achieve by recycling of tags. However, their multiple use causes that RFID tags are placed repeatedly on a surface of identified object and then, peeled off. Thus, tags have to withstand even long-term mechanical exposure in order to guarantee reliable work in a long period of time. In this paper, reliability of UHF tags under long-term mechanical cycling is reported. Two different RFID tags were used to perform investigations which revealed that mechanical properties of tested RFID tags are mostly dependent on their stackup, i.e. additional top and internal foil or paper layers may introduce significant growth of mechanical durability of the tested RFID tag samples.     

100 ps waveguide multiple quantum well (MQW) optical modulator with 10:1 on/off ratio

By incorporating two quantum wells into a capillary waveguide, we have made the first MQW optical modulator with an on/off ratio of at least 10:1. Furthermore, this device was used to generate an optical pulse less than 100 ps long, the fastest to date with an MQW device.     

Fatigue-creep crack propagation path in solder joints under thermal cycling

The present study investigates the thermal fatigue crack propagation path in a eutectic solder joint between a 2512 leadless chip resistor and a printed wiring board which had experienced thermal cycling between -55 and 125°C. This was achieved through the microstructural examination of fractured surfaces of the joints. Patches of finely spaced striations were observed in a predominant shear strain field in the joints. These striations were attributed to the tensile strain components in the field and used to add the identification of the fatigue crack propagation direction. It was observed that cracks did not simply propagate across the depth of the joint from the inner end (the heel) to the outer end (the toe) in the longitudinal direction, but from a corner point on the free edge of the heel to the center across the joint depth, making an angle of about 70° with respect to the longitudinal direction.     

热循环条件下Sn基钎料接头电迁移行为研究

通过电迁移和热疲劳循环实验,研究了热循环和高电流密度耦合作用下Sn58Bi和Sn3.0Ag0.5Cu钎料焊接接头的失效形式。实验结果表明,在通电和高低温冲击的耦合作用下,两种钎料接头的失效都发生在升温阶段。热循环导致接头内部裂纹的萌生和扩展,导致局部电流密度持续增大,加速了电迁移的发生,最终导致焊点失效。在热电耦合作用下,Sn58Bi钎料接头的使用寿命要长于Sn3.0Ag0.5Cu钎料接头的使用寿命。     

具有多个点损耗的DFRA开关增益定量分析模型

基于忽略泵浦光损耗的正向拉曼光纤放大器耦合方程,推出光纤中存在多个熔接(点)损耗情况下正向(及反向)泵浦光的分布式拉曼光纤放大器(DFRA)增益的定量分析模型,进而推出由不定长光纤小段、且各小段增益系数不同、各小段之问存在熔接(点)损耗DFRA增益的定量分析模型。并针对DWDM系统的增益模型,在考虑了熔接点对信号光之间产生的泵浦作用的损耗,将上述模型进行了修订。上述两种情况下的模型,较之以往的定性的分析文献[3][4]给出定量分析公式和明确的物理解释,并指出熔接损耗点越靠近泵浦光的输入端,对DFRA拉曼开关增益的影响越大(使其越小)。为了考查模型的正确性及适用性,由具有泵浦光之间、信号光之间、泵浦光及信号光之间反相DFRA耦合方程的仿真程序进行了验证,误差不超过0.02dB。最后得出对实际DFRA设计十分有益的结论:当每3公里一个熔接点损耗系数小于0.092dB 时(实际系统中最坏情况下损耗有0.1dB),跨距小于120公里的拉曼光纤放大器的开关增益较无熔接点损耗时下降小于10%。这说明在已铺设的光纤传输系统中使用拉曼放大器是可行的,本文中具有点损耗的DFRA开关增益公式可作为实际DFRA系统设计参考标准。     

Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.     

用处理器的一个引脚控制开／关功能

最近的设计实例促使我提供一个曾用于某个项目的较为简单的解决方案(参考文献1).我们需要做一个受处理器监控的瞬时电源开关.这种监控能使处理器在按下电源开关后推迟节电请求,到所有程序都正常退出为止.另外,处理器可以在不工作期间切断电源,以延长电池寿命.该项目还需要一个升压变换器,用以将两至三节AA电池电压转换为5V.本设计使用的IC1是德州仪器公司(www.ti.com)生产的TPS61032型升压变换器(图1).它带有一个使能引脚(第9引脚),该管脚在其电位被拉低时,不仅关断变换器电源,还将负载与电池完全断开.处理器是PIC16F874.本设计的关键是,先将处理器的I/O引脚配置成输出端,以保持变换器的使能引脚为高电平,然后再重新配置以检测电源开关的逻辑电平.