Optimization of CORDIC cells in the backward circular rotation mode

The COordinate Rotation DIgital Computer (CORDIC) algorithm in the backward circular rotation mode efficiently computes phase estimation. In this letter, a set of new rules are proposed to design a CORDIC processor to achieve a given signal-to-noise ratio (SNR). To this end, two new approximate expressions to estimate the SNR are derived accounting for the approximation and quantization errors, respectively.     

Fixed-point error analysis of CORDIC processor based on the variance propagation formula

This paper presents a fixed-point mean-square error (MSE) analysis of coordinate rotation digital computer (CORDIC) processors based on the variance propagation method, whereas the conventional approaches provide only the error bound which results in large discrepancy between the analysis and actual implementation. The MSE analysis is aimed at obtaining a more accurate analysis of digital signal processing systems with CORDIC processor, especially when the design specification is given by the signal-to-noise ratio or MSE. For the MSE analysis, the error source and models are first defined and the output error is derived in terms of MSE in the rotation mode of the conventional CORDIC processor. It is shown that the proposed analysis can also be applied to the modified CORDIC algorithms. As an example of practical application, a fast Fourier transform processor using the CORDIC processor is presented in this paper, and its output error variance is analyzed with respect to the wordlength of CORDIC. The results show a close match between the analysis and simulation.     

流水线结构A/D转换器的算法改进

为了减小流水线结构A/D转换器的量化误差,提出了一种简单有效的改进算法。该算法在不附加任何额外电路的情况下,通过对模拟量化比较电平的调整,实现了舍入式流水线结构,其量化误差范围在-1／2LSB与1／2LSB之间。提出了改进算法的简化结构,并作了分析。利用MATLAB完成了算法仿真,证明该算法满足舍入式的要求,且适用于任何位数的流水线结构．     

Numerical Accuracy of Fast Fourier Transforms with CORDIC Arithmetic

The vector rotation operation in the butterfly of a Fast Fourier Transform (FFT) can be calculated by a complex multiplier as well as a CORDIC (COordinate Rotation DIgital Computer). For these vector rotation blocks, expressions for the maximum numerical error are derived. It is shown that the error introduced by the CORDIC can be reduced by increasing the size of the input vector of the CORDIC and decreasing the size of the output vector by the same amount. This input vector scaling makes the reduction possible of the number of bits in the data path of the CORDIC. The impact on the Signal to Noise Ratio (SNR) of the FFT is evaluated when a CORDIC is applied in the FFT butterfly.     

基于流水线CORDIC算法的数字下变频实现

数字下变频的FPGA实现通常都是基于查表的方法，为了达到高精度要求，常常需要耗费大量的ROM资源去建立庞大的查找表。文中提出了一种基于流水线CORDIC算法的数字下变频实现方案，可有效地节省FPGA的硬件资源，提高运算速度。文章最后给出了该方案的精度分析和实验的仿真结果。     

Radix-4 Vectoring CORDIC Algorithm and Architectures

In this work we extend the radix-4 CORDIC algorithm to the vectoring mode (the radix-4 CORDIC algorithm was proposed recently by the authors for the rotation mode). The extension to the vectoring mode is not straightforward, since the digit selection function is more complex in the vectoring case than in the rotation case; as in the rotation mode, the scale factor is not constant. Although the radix-4 CORDIC algorithm in vectoring mode has a similar recurrence as the radix-4 division algorithm, there are specific issues concerning the vectoring algorithm that demand dedicated study. We present the digit selection for nonredundant and redundant arithmetic (following two different approaches: arithmetic comparisons and table look-up), the computation and compensation of the scale factor, and the implementation of the algorithm (with both types of digit selection) in a word-serial architecture. When compared with conventional radix-2 (redundant and non-redundant) architectures, the radix-4 algorithms present a significant speed up for angle calculation. For the computation of the magnitude the speed up is very slight, due to the nonconstant scale factor in the radix-4 algorithm.     

CORDIC算法基本原理研究

函数的FPGA实现通常都是基于查表的方法,为了达到高精度要求,常常需要耗费大量的ROM资源去建立庞大的查找表。文中探讨了的CORDIC算法与其基本原理,可有效地节省FPGA的硬件资源,提高运算速度。     

A Modified CORDIC FPGA Implementation for Wave Generation

This paper presents a modified coordinate rotation digital computer (CORDIC) algorithm implemented in parallel architecture to generate sine and cosine waveform. Since CORDIC is a combination of only additions and shifts, it can be efficiently implemented in hardware. The proposed algorithm further approximates the way of computing rotation angle based on Taylor series in order to reduce the usage of Read-Only-Memory (ROM) table. Thus area and power is reduced due to partial usage of ROM storage. The precision remains the same as the original algorithm. The modified 32-bits pipeline CORDIC are implemented in Spartan XC3S500E device using Xilinx ISE 12.3 design suite. The result is compared with original CORDIC and Xilinx coregen in device utilization. It is shown that the logic usage is 31 FFs and 285 FFs less than the original design and Xilinx core, respectively. When compared with the original design, the signal power and total power reduction at 40 MHz clocks are 7.69 % and 1.35 %, respectively. The bit error remains at 10^?8 dB level. The SNR of modified CORDIC is about 2 dB lower, which is acceptable in wave generation.     

一种改进超四算法的DDS设计

为了提升直接数字频率合成器(Direct Digital Synthesizer,DDS)的性能,针对DDS的相幅转换器进行了改进。基于坐标旋转数字计算算法(Coordinate Rotation Digital Computer Algorithm,CORDIC),利用三角函数角度近似的性质和相位寻址位与旋转角度的转换关系对超四算法改进,得到了仅需一次单向旋转的改进算法,并给出了该算法实现的电路结构。通过Matlab仿真分析,该电路无杂散动态范围值可以达到-119. 1 dBc,输出误差小于1. 05×10-5。基于Xilinx的FPGA平台进行仿真实验,结果表明该电路结构的输出延时不超过21 ns,相比其他类型的CORDIC算法提升了近48!的速度,同时面积资源也明显减少。该设计可以为雷达、通信等系统优化提供新的思路。     

Very-High Radix CORDIC Rotation Based on Selection by Rounding

A very-high radix algorithm and implementation for CORDIC rotation in circular and hyperbolic coordinates is presented. The selection function consists of rounding the residual. It is shown that this assures convergence from the second iteration on. For the first iteration, the selection is done by table, using a lower radix than for the remaining iterations. The compensation of the variable scale factor is done by computing the logarithm of the scale factor and performing the compensation by an exponential. Estimations of the delay for 32-bit and 64-bit precision show a substantial speed up when compared to low radix implementations. The proposed algorithm is also compared with previously proposed very-high radix ones, and significant advantages are identified.     

A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 μm CMOS

The paper describes the implementation of a 380 MHz, 13 bit, direct digital synthesizer/mixer IC in 0.25mum CMOS technology. The circuit employs an innovative architecture which divides the pi/4 rotation operation required in the quadrature synthesizer/mixers, in three rotations. The first two rotations are implemented by using a CORDIC datapath completely realized in carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation, and a multiply by constant and addition circuit for the second rotation. The final (third) rotation is multiplier-based, in order to reduce the circuit latency and increase the circuit performances. The CORDIC datapath is implemented with a novel approach both at the algorithmic level and at the transistor level. At the algorithmic level the combined employ of sign-extension prevention, overflow prevention and a novel rounding scheme are presented. At the transistor level a design style that jointly uses full-CMOS and DPL to improve the circuit latency is described. The overall circuit performances are very interesting. The synthesizer/mixer IC, realized in a 0.25 mum CMOS technology, has an area occupation of 0.22 mm² and dissipates 152 mW at 380 MHz with a supply voltage of 2.5 V     

Mixed-radix,virtually scaling-free CORDIC algorithm based rotator for DSP applications

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.     

CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation

—In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power-of-two point DCT, and develop its corresponding efficient VLSI implementation. The proposed algorithm has some distinguish advantages, such as regular Cooley-Tukey FFT-like data flow, identical post-scaling factor, and arithmetic-sequence rotation angles. By using the trigonometric formula, the number of the CORDIC types is reduced dramatically. This leads to an efficient method for overcoming the problem that lack synchronization among the various rotation angles CORDICs. By fully reusing the uniform processing cell (PE), for 8-point DCT, only four carry save adders (CSAs)-based PEs with two different types are required. Compared with other known architectures, the proposed 8-point DCT architecture has higher modularity, lower hardware complexity, higher throughput and better synchronization.     

一种CORDIC算法的精度分析及其在FFT设计中的应用

针对CORDIC算法的精度问题进行了理论分析，首先研究了CORDIC算法中旋转级数、操作数位宽与精度的关系，并将这一结果实际应用于FFT算法的FPGA设计实现中。经实际验证，这种分析的结果是合理的，可作为设计过程中选取旋转级数和操作数数据位宽的参考。     

Digital Synthesizer/Mixer With Hybrid CORDIC–Multiplier Architecture: Error Analysis and Optimization

This paper describes a novel architecture for digital synthesizer/mixer (DSM). The operation performed by a DSM corresponds to a rotation of the input vector in the complex plane. The proposed architecture divides this rotation into three subrotations. The first one uses a few CORDIC stages, in which the rotation directions are in parallel computed with the help of a small lookup table. The CORDIC algorithm is employed also in the second subrotation, where the rotation directions are readily available after a simple recoding of the bits of the residual angle. The final rotation is multiplier based to reduce circuit latency and increase performances. A detailed error analysis and sizing methodology is given in this paper. It is shown that different versions of the architecture can be conceived by varying the dimensions of the second block and the topology of the third block. The proposed architecture exhibits very good performances, owing to the efficient carry–save implementation of CORDIC datapaths, the reduced lookup table, and the small size of multipliers. Implementations in a 0.25- ${rm mu}hbox{m}$ CMOS technology are presented in order to demonstrate the design methodology and to investigate the implementation tradeoffs.      

Configurable Floating-Point FFT Accelerator on FPGA Based Multiple-Rotation CORDIC

Fast Fourier transform (FFT) accelerator and Coordinate rotation digital computer (CORDIC) algorithm play important roles in signal processing.We propose a conflgurable floating-point FFT accelerator based on CORDIC rotation,in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory.To finish CORDIC rotation efficiently,a novel approach in which segmentedparallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration.To prove the efficiency of our FFT accelerator,four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT.Experimental results show that our structure,which is composed of four butterfly units and finishes FFT with the size ranging from 64 to 8192 points,occupies 33230(3％) REGs and 143006(30％)LUTs.The clock frequency can reach 122MHz.The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4.What's more,only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.     

Quantization and other nonlinear effects in the LMS adaptive algorithm

Quantization effects in the complex_lms adaptive algorithm are studied for two cases. For frequency domain adaptation, the complex scalarlms algorithm is analyzed by modeling the accumulator input quantizer as a memoryless nonlinearity. For time domainlms adaptation, weight vector adaptation is studied by adding of dither. The dither linearizes the rounding quantizer at each accumulator input. The effects of both the dither and quantization noise on algorithm performance are studied. Results are also presented for an arbitrary nonlinear operation on the data input to the weight update for the real lms algorithm with a gaussian data model. Difference equations are derived and solved for the weight first and second moments. The solutions are used to minimize the mean square error over the choice of nonlinearity for a fixed transient behaviour.     

CORDIC-based VLSI architectures for digital signal processing

The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms     

一种基于SystemVerilog的CORDIC算法IP核实现方案

CORDIC是一种坐标旋转算法,常用来计算向量旋转、三角与反三角函数以及数乘、除法等初等函数值。但是,由于它的形式多样,在FPGA硬件实现时,常规做法是根据不同计算需求设计特定的RTL代码,导致灵活性和可移植性受到了极大限制。因此,根据CORDIC各种运算形式的特点,利用SystemVerilog语言实现了CORDIC算法通用IP核制作,大大提高了代码的灵活性和可移植性,并且在FPGA中得到了仿真验证。     

Comparison of random phasing methods for reducing beam pointing errors in phased array

Beamsteering for phased arrays normally causes a pointing deviation of the main beam due to the periodic phase quantization error across the array. This deviation occurs due to the use of digital phase shifters. We modify the random phasing methods into appropriate random phasing methods, in which the accuracy of the pointing direction in phased arrays is improved. The word "appropriate" means that, for the phase quantization error, the rounding to the nearest bit method is not always to be applied, nor is the random phasing method. An appropriate mean phase error equal-to-zero method (AMPEEZ), an appropriate two probable value method (A2PV) and an appropriate phase-added method (APAM) are proposed. These methods are simulated and compared with the nonappropriate ones.