Two methods of decomposition symbolic simulation of circuit functions

A decomposition method of total algebraic complements with “screening” and the topology transformation method have been proposed for symbolic simulation of circuit functions. They are based on decomposition of the simulated circuit and the use of index operations in calculating the model matrix determinant and algebraic complements of its elements.     

Analog circuit design optimization based on symbolic simulation andsimulated annealing

A methodology for the automatic design optimization of analog integrated circuits is presented. A non-fixed-topology approach is realized by combining the optimization program OPTIMAN with the symbolic simulator ISAAC. After selecting a circuit topology, the user invokes ISAAC to model the circuit. ISAAC generates both exact and simplified analytic expressions, describing the circuit's behavior. The model is then passed to the design optimization program OPTIMAN. This program is based on a generalized formulation of the analog design problem. For the selected topology, the independent design variables are automatically extracted and OPTIMAN sizes all elements to satisfy the performance constraints, thereby optimizing a user-defined design objective. The global optimization method used on the analytic circuit models is simulated annealing. Practical examples show that OPTIMAN quickly designs analog circuits, closely meeting the specifications, and that it is a flexible and reliable design and exploration tool     

Improvements in hierarchical symbolic tolerance and sensitivityanalysis

Sensitivity and tolerance analyses are important for circuit optimisation, but unfortunately very time consuming. In recent years new hierarchical symbolic methods have been developed for large linear circuits. These approaches make symbolic techniques a worthwhile alternative to classical numerical methods. Using the hierarchical symbolic approach, a new strategy is introduced which significantly reduces the computational expense of sensitivity and tolerance analyses compared to previous procedures     

A spatially layered hierarchical approach to video coding

Layered techniques offer attractive features for video coding in several applications including high definition TV (HDTV). After describing these in general, we propose an approach in which the layering is performed in the pel domain using a modified version of the conventional spatial pyramid technique. Comparisons are made with the alternative methods of subband coding and layering of DCT coefficients. Results with HDTV pictures were first demonstrated on 3 November 1992.     

A hierarchical approach to feature extraction and grouping

In this paper, the problem of extracting and grouping image features from complex scenes is solved by a hierarchical approach based on two main processes: voting and clustering. Voting is performed for assigning a score to both global and local features. The score represents the evidential support provided by input data for the presence of a feature. Clustering aims at individuating a minimal set of significant local features by grouping together simpler correlated observations. It is based on a spatial relation between simple observations on a fixed level, i.e., the definition of a distance in an appropriate space. As the multilevel structure of the system implies that input data for an intermediate level are outputs of the lower level, voting can be seen as a functional representation of the "part-of" relation between features at different abstraction levels. The proposed approach has been tested on both synthetic and real images and compared with other existing feature grouping methods.     

Analytical nonlinear HEMT model for large signal circuit simulation

A new nonlinear high electron mobility transistor (HEMT) model based on the Curtice model is described. This model introduces terms for the leakage current for subthreshold bias, drain voltage dependencies of knee voltage, drain conductance and threshold voltage, transconductance enhancement at high frequencies caused by DX centers, and the bias dependence of capacitance. Applying this model to pseudomorphic double-recessed gate HEMT's gives an average error of 2.6% for DC current and 10% for S-parameters     

A hierarchical reliability analysis for circuit design evaluation

We suggest a computationally efficient and flexible strategy for assessment of reliability of integrated circuits. The concept of hierarchical reliability analysis proposed relies on doing reliability assessments during the design and layout process [reliability computer aided design (RCAD)]. Design rules are suggested based on calculations of steady-state mechanical stresses built up in interconnect graphs and trees due to electromigration. These design rules identify a large fraction of interconnect graphs in a typical design as immune to electromigration-induced failure. The stated design rules are an extension of the Blech-length concept to interconnect graphs. Our suggested new strategy will have important implications for design and layout processes as design limits for a given technology are reached     

Formula approximation for flat and hierarchical symbolic analysis

This paper addresses the topic of reducing the complexity of formulae resulting from the symbolic analysis of analog integrated circuits, covering both flat and hierarchical symbolic analysis approaches. Previously reported criteria for flat analysis are first briefly reviewed and their limitations illustrated via examples of practical analog circuits. In all of these criteria simplifications are performed by estimating the numerical values of the symbolic terms at a single point of the parameter space, corresponding to the expected typical values for symbols. Consequent quantitative as well as qualitative inaccuracies resulting from this approach are identified. A new simplification strategy for flat symbolic approaches is then presented in which insignificant terms are deleted taking into account expected ranges of variation in the symbol values. Examples are used to show that this new criterion overcomes the drawbacks encountered in previous ones. Finally, an algorithm to simplify hierarchical formulae is presented which includes consideration of the potential ranges of variation in the symbolic parameter values. This algorithm is also applied to practical analog integrated circuits.1. Most of the results in this paper have been obtained with a 4-Mips and 8-Mbyte physical memory SUN3/260 workstation.2. In the rest of the paper the concept offormula complexity denotes the number of symbolic terms contained in a formula. Each addend in (4) is considered as a term to this purpose.3. For instance, simplification of the voltage gain for the folded cascode OTA of figure 1b, with a maximum error margin of 60% ( _M = 0.6), yields a dc gain deviation of 1.6% [9].4. An analog schematic is said to be sized when a numerical value has been assigned to each circuit element and model parameter.5. In practice a sufficiently fine grid should be defined inside that region.6. Here, symbol is generally applied, in the sense that it may either denote a parameter space variable, a product of variables, or a sum of products.7. The models used in this example are intended only as an illustration. Hence, they do not include all the issues required for practical transconductance amplifier applications.     

A hierarchical approach to color image segmentation using homogeneity

In this paper, a novel hierarchical approach to color image segmentation is studied. We extend the general idea of a histogram to the homogeneity domain. In the first phase of the segmentation, uniform regions are identified via multilevel thresholding on a homogeneity histogram. While we process the homogeneity histogram, both local and global information is taken into consideration. This is particularly helpful in taking care of small objects and local variation of color images. An efficient peak-finding algorithm is employed to identify the most significant peaks of the histogram. In the second phase, we perform histogram analysis on the color feature hue for each uniform region obtained in the first phase. We successfully remove about 99.7% singularity off the original images by redefining the hue values for the unstable points according to the local information. After the hierarchical segmentation is performed, a region merging process is employed to avoid over-segmentation. CIE(L*a*b*) color space is used to measure the color difference. Experimental results have demonstrated the effectiveness and superiority of the proposed method after an extensive set of color images was tested.     

Equivalent circuit approach for single electron transistor modelfor efficient circuit simulation by SPICE

A new compact DC/transient single electron transistor model for circuit simulation by SPICE is introduced. This model includes newly developed equivalent circuit approach based on the time-dependent master equation and an exact conductance or transient conductance model. The simulation speed of this model is improved compared with that of the previous models     

A hierarchical learning approach to anti-jamming channel selection strategies

Wireless Networks - This paper investigates the channel selection problem for anti-jamming defense in an adversarial environment. In our work, we simultaneously consider malicious jamming and...     

A hierarchical approach to position-based multicast for mobile ad-hoc networks

In this paper we present Scalable Position-Based Multicast (SPBM), a multicast routing protocol for ad-hoc networks. SPBM uses the geographic position of nodes to provide a highly scalable group membership scheme and to forward data packets in a way that is very robust to changes in the topology of the network. SPBM bases the forwarding decision on whether or not there are group members located in a given direction, allowing a hierarchical aggregation of membership information. The farther away a region is from an intermediate node, the higher the level of aggregation for this region should be. Because of aggregation, the overhead for group membership management scales logarithmically with the number of nodes and is independent of the number of multicast senders for a given multicast group. Furthermore, we show that group management overhead is bounded by a constant if the frequency of membership updates is scaled down with the aggregation level. This scaling of the update frequency is reasonable since the higher the level of aggregation is, the lower the number of membership changes for the aggregate will be. The performance of SPBM is investigated by means of simulation, including a comparison with ODMRP, and through mathematical analysis. We also describe an open source kernel implementation of SPBM that has been successfully deployed on hand-held computers.     

A circuit approach to SAW filterbanks for frequency synthesis

A SAW filterbank (2.5 × 0.9 cm) coupled to a miniature silicon-on-sapphire (SOS) p-i-n diode, multiple-input single-output RF switch array (2.5 × 0.25 cm) forms the basis of a very compact UHF frequency synthesizer. In this paper the operation, design, fabrication, and performance of rapid-switching SAW frequency synthesizers is described. Experimental measurements depicting the spectral purity of the waveforms synthesized by two devices; one fabricated on LiTaO3and the other on AlN-on-sapphire, operating over respective frequency ranges of 520-650 MHz and 970-1210 MHz are provided.     

用Nullor构建理想电压源模型求解符号传递函数的方法

电路网络的符号传递函数分析技术在电路分析与设计中起着重要的作用。本文利用Nullor元件，构建了理想电压源的模型，扩展了节点分析法的应用范围，并且基于Mathematica强大的符号处理能力，设计出一种求解网络符号传递函数的节点分析法。该方法可以求解节点间含有理想电压源的线性时不变（LTI）系统中各种电路参数的符号传递函数。电路分析与设计实例表明，利用本文给出的方法所开发的符号传递函数求解程序，是电路分析和电路设计的有利助手。     

A circuit for floating inductance simulation

An active RC realization of a lossy floating inductor is presented. The circuit uses two operational amplifiers--each in the unity gain connection--three resistors, and two capacitors, and has low L and Q sensitivities to passive as well as active components.     

基于矢量量化的层次分形编码方法

文中提出了一种新的分形图像压缩方法,该方法将矢量量化的概念应用于分形块编码中,对图像的平缓区进行矢量量化的线性组合编码,对图像的丰富细节区用分形编码,并且在分形编码时,采取了层次处理。实验表明,与基本的分形块编码方法相比,本文提出的矢量量化层次分形编码方法在保证一定的重建图像质量下,使图像的压缩比有了明显的提高,并且大大提高了编码和解码速度。