A low-power scan driver employing IZO TFTs including an AC–DC type output module

This paper presents a low-power and simple scan driver with a new output module called as AC–DC type output module. 46 stages of the scan driver are fabricated by integrating In–Zn–O Thin-film transistors (IZO TFTs) with back channel etch (BCE) structure on the glass substrate. Under 100 hours’ test, it is shown that the voltage fluctuation of the output signal can be well suppressed by the proposed AC–DC type output module up to the whole 46 stages. The power consumption can be obviously reduced by using the AC–DC type output module compared with the conventional AC–AC type output module. It is measured that the power consumption of one stage for the proposed scan driver with AC–DC type output module at the clock frequency of 16.7 kHz is 170 μW, as well as 393 μW for the proposed scan driver with the conventional AC–AC type output module. It is shown from the simulation results that there is a good tradeoff between the power consumption and the rising time for the proposed AC–DC type output module compared with AC–AC type output module and DC–DC type output module.     

Characteristics of a‐IZO TFTs with high‐κ HfSiOx gate insulator annealed in various conditions

In this work, we investigate the enhanced performance of amorphous indium zinc oxides‐based thin film transistors with hafnium silicate (HfSiO_x) gate insulators. HfSiO_x gate insulators annealed at various conditions are deposited by cosputtering of hafnium oxide and Si. The structural properties of HfSiO_x are investigated using the atomic force microscopy, X‐ray diffraction, and x‐ray photoelectron spectroscopy (XPS). techniques. Furthermore, the electrical characteristics of HfSiO_x are analyzed to investigate the effect of annealing conditions. We obtain optimal results for thin film transistors with HfSiO_x gate insulators annealed for 1 h at 100 °C, with a saturation mobility of 1.2 cm²/V · s, threshold voltage of 2.2 V, on current/off current ratio of 2.0 × 10⁶, and an insulator surface roughness of 0.187 nm root mean square.     

Characteristics of polycrystalline Si TFTs fabricated on glass substrates by excimer laser annealing with nickel-sputtered amorphous Si films

We have fabricated two kinds of thin film transistors (TFTs) on the glass substrates using polycrystalline silicon (poly-Si) thin films with small and large grain sizes processed by Excimer Laser Annealing (ELA) and carried out a comparative analysis. The grain size was controlled by nickel atom content in amorphous silicon (a-Si) thin films. With increasing grain size of poly-Si thin films, the carrier mobility increased from 40.8 to 54.4 cm²/V s and the absolute value of threshold voltage reduced from 2.1 to 1.5 V. The observed improvements in the electrical characteristics of poly-Si TFTs are attributed mainly to the reduction of defect density rendered by large grain size. These observations indicate that the sputtered nickel atom content in a-Si layer is a key parameter in determining the characteristics of ELA processed TFTs fabricated on the glass substrates.     

Bezel free design of organic light emitting diode display via a‐InGaZnO gate driver circuit integration within active array

In this article, we described an innovative design technology of active matrix organic light emitting diode (AMOLED) display, to provide a bezel free design. We designed gate driver circuit of amorphous indium‐gallium‐zinc oxide thin‐film transistors (TFTs) not on the bezel area but within the active array. Although we applied challengeable design, no degradation of electrical/optical properties of panel was observed. Because we effectively prevented capacitive coupling and interference between the emission circuit and integrated gate driver circuit in active array, finally, we successfully demonstrated a bezel free designed AMOLED display of 18.3″ HD (1366 × 768) driven by a‐InGaZnO TFTs.     

基于PCI总线的高速数据采集设备驱动开发

基于PCI总线的高速数据采集设备驱动开发,其核心问题是驱动程序必须要有快速的实时响应能力和灵活的数据接收结构。分析了限制驱动程序高速数据传输的瓶颈,提出了分片、分帧的数据传输结构,给出了基于该结构的设备驱动设计思路。数据传输速率可达85MBps,与计算机的配置无关。     

一种彩色LED显示屏16位恒流驱动专用芯片的设计

基于CSMC 0.5μm 5 V CMOS标准工艺,流片实现了一种彩色LED显示屏16位恒流驱动专用芯片的设计。采用高精度的基准电源抗失调和驱动电流输出匹配等技术,保证了在-40℃～80℃工作温度、4.5 V～7 V工作电压和负载宽幅改变情况下,芯片各通道最大输出电流达到106 mA,而相应的位间电流输出误差小于2.1%,片间电流输出误差小于3.3%。同时电源电压调整率为0.3%,输出电压调整率为0.09%。     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Two‐stage degradation in n‐channel LTPS‐TFTs under negative and positive bias stresses

Device degradation behaviors of n‐channel low‐temperature polycrystalline silicon thin film transistors under negative bias stress and positive bias stress were investigated. It was found that the threshold‐voltage has a two‐stage degradation, shifting to different direction with time. The mobility and the subthreshold swing SS both show a dependence on the stress time. It was determined that the interface trap states, the grain boundary trap states, and electron trapping together dominate the time‐dependent degradation behaviors. The trap is caused by the rupture of Si─H and Si─O bonds. A comprehensive model is proposed to explain the time‐dependent degradation behaviors clearly. In addition, after removing the stress, the recovery behaviors of threshold voltage V_th can be observed, which provide the evidence supporting the degradation model proposed.     

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.     

电子纸显示器驱动程序的设计与实现

电子纸显示器(EPD)能展现良好的阅读舒适性,但它具有显示速度慢的缺点,这必须通过对显示驱动程序进行优化设计加以克服。提出了一种基于三缓冲区的EPD驱动程序的实现架构和设计方法,并在一个专用阅读设备上进行了实现和验证。与传统的双缓冲机制相比,三缓冲架构增设了一个EPD显示区,用于保存显示到屏幕上的数据帧。测试结果表明,该驱动程序工作正常,不会出现屏幕闪烁问题,显示效果良好,用户可以获得较佳的视觉体验。     

A 13‐bit universal column driver for various displays of OLED and LCD

A universal column driver is implemented in a 0.13‐µm high‐voltage CMOS process for not only TFT‐LCD but also OLED applications. The proposed column driver employs 13‐bit linear DAC to cover all gamma curves of display applications and address‐based configuration for intra‐ panel interface protocol to support both TV and IT applications. Measured results demonstrate the average voltage of output channels (AVO) is under 1mv, which satisfies 1‐LSB resolution at 18.5V of AVDD.     

A small‐area and low‐power data driver IC using two‐stage DAC with a capacitor array for active matrix flat‐panel displays

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/?0.52 least significant bit and +0.62/?0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

高频移相全桥变换器的数字驱动研究

基于经典全桥零电压零电流开关(ZVZCS)变换器拓扑,采用数字信号处理器(DSP)进行控制,提出了一种新型的移相PWM波形产生算法。结合IR公司最新推出的集成驱动芯片IR2304,通过对传统驱动电路增加两个无源元件,设计了带有负电压关断的硬件驱动电路,克服了IR系列不能产生关断负电压的缺点。实验验证了新型算法的正确性和驱动系统设计的可行性。     

动态源路由协议DSR在NDIS架构中的设计与实现*

研究分析了基于Windows NDIS框架构建无线移动Ad hoc网络路由协议测试平台的一般方法,提出了以NDIS中间层驱动形式创建动态源路由协议(dynamic source routing,DSR)的设计方案,有效地解决了嵌入NDIS的DSR协议栈与Windows操作系统既有TCP/IP协议栈以及厂商网卡驱动之间的衔接与交互等关键问题,并最终完成了该DSR协议栈的实现。实验结果表明,该DSR协议栈的设计切实可行,通过在真实环境中的运行测试,为进一步分析研究DSR的安全、优化和应用提供了实体测试平台。     

基于FPGA的高速高密度PCB设计中的信号完整性分析

根据摩尔定律,高速高密度印刷电路板(PCB)的设计变得越来越复杂。针对大型或特大型高速高密度PCB设计中信号完整性的一些关键问题,如：PCB层叠、传输线类型、特征阻抗计算、互连拓扑结构、端接技术、延迟匹配、串扰分析、差分布线等,通过理论分析、仿真验证、工程实践相结合的方式进行讨论,并给出相应的解决方法或设计规则。在此基础上,给出现场可编程门阵列(FPGA)多层PCB板设计原则。具体工程实验证明,在这些规则或机制的驱动下,高速高密度PCB的设计能够获得良好的实际效果。     

高速球形摄像机PTZ跟踪策略设计及实现

针对智能监控中基于高速球形摄像机的PTZ跟踪功能模块,设计了一种PTZ跟踪控制策略。该策略在球机机械参数未知的情况下,一方面能控制球机实时地跟踪目标使目标始终处于视野中央,另一方面可自动进行变倍动作来放大拍摄目标的局部细节。针对球机Zoom控制中跟踪窗口大小自适应调整的问题,利用SIFT算法设计了一种计算球机变倍率的方法。利用VS2005和OpenCV软件平台实现了PTZ跟踪的整体流程。实验表明,该策略能有效、稳定地进行PTZ跟踪。     

一种基于FPGA的高速自整角机数字解算方法

自整角机是广泛应用于轴角测量系统中一种非常重要的测量元件,现场可编程逻辑门阵列(FP-GA)技术近几年的发展使得利用硬件描述语言实现信号的快速实时处理成为可能。设计采用Spartan-3系列的XC3S400芯片,根据自整角机输出信号的特点和角度测量原理,利用Verilog HDL语言编程完成控制逻辑和自整角机角信息的解算。应用坐标旋转数字计算机(CORDIC)算法在FPGA中实现了反正切函数的计算,并引入改进的CORD IC算法以提高运算速度,节省硬件资源。经过测试,达到0.01°的轴角解算精度,角度解算区间达到[-360°,360°],并且,在不同的角度偏移量和不同的轴初始位置情况下都能获得满意的结果。     

基于高速DSP技术的低成本智能焊接机器人设计与研究

针对目前工业化焊接存在工作繁重、人员劳动强度大、身体容易疲劳、易出错、安全生产事故率较高、焊接质量难以保证等问题,基于国外进口通用焊接机器人价格昂贵、维护保养成本高、备品备件难选购等情况,提出一种高速DSP（数字信号处理器）的低成本智能焊接机器人解决办法,深入研究了机器人各关键部件和核心技术,搭建了机器人硬件平台,设计了专用运动控制器,分析了人工引导方式“示教-编程”操作学习方法,应用大量工业成熟货架产品,实现了专用智能化焊接机器人,制造了国产化样机并投产实机对比验证,可原位替代昂贵进口设备,提高产品焊接质量,减少人工出错率,降低工人劳动强度,节约设备采购维护成本,提高劳动生产率。     

面向卷积神经网络的高并行度FPGA加速器设计

大多数基于卷积神经网络(CNN)的算法都是计算密集型和存储密集型的,很难应用于具有低功耗要求的航天、移动机器人、智能手机等嵌入式领域.针对这一问题,提出一种面向CNN的高并行度现场可编程逻辑门阵列(FPGA)加速器.首先,比较研究CNN算法中可用于FPGA加速的4类并行度;然后,提出多通道卷积旋转寄存流水(MCRP)结...