A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

Evaluation of P-HEMT MMIC technology PH25 for space applications

The evaluation of the P-HEMT technology PH25 according to the European Space Agency requirements is presented. The reliability assessment plan features high temperature storage tests, DC life-tests and RF life-tests, performed on a set of evaluation test vehicles specifically defined for this purpose. The results of these tests evidence a temperature activated wear-out mechanism, a very low sensitivity of PH25 on strong RF stress and no sensitivity on hydrogen. Failure rates calculations are in line with the space programme requirements.     

X波段功率单片放大器的研制

介绍了X波段功率单片放大器的设计、制造、测试等技术,以及器件的大信号模型的建立.X波段功率单片放大器采用两级放大,经过功率分配和功率合成,输入输出匹配为50 Ω,单片性能达到输出功率≥5W,附加效率≥33%,功率增益≥13.5dB,增益波动≤0.3dB,输入驻波比≤2?1.     

A new MMIC sampling phase detector design for space applications

A new sampling phase detector monolithic microwave integrated circuit (MMIC) using a standard 0.18-/spl mu/m GaAs technology has been designed and tested. The authors emphasize that commutation time has to be taken into account rather than pulse duration, as done in previous presented works. Thus, the new SPD design concept eases command-signal generation. It also solves the tradeoff between phase detection and RF signal input-to-output isolation through the use of a double sampler topology and a proper command-signal generation. It has been designed taking care of space level specifications and environment. Phase detection level above 2 V/sub pp/ and operating frequencies up to 20 GHz have been measured, although higher frequency operation can be expected.     

Fast response phase detector for a phase-locked loop

A new phase detector that can measure the phase difference of sinusoidal or square wave signals and represent it as a DC output voltage is proposed. The proposed detector can distinguish phase leading or phase lagging by using output voltage polarity. This detector is implemented by an analogue electronic circuit without using the low-pass filter, and its detection lime is not more than a half-cycle. This performance is superior to conventional phase detectors. Additionally, its linear characteristic is good.     

Synthesis of a two-discriminator phase-locked loop circuit

A new phase-locked loop circuit that is a system of two discriminators is described. One of the discriminators is used in the phase-tracking loop, and the other is used in the loop of the cycle-slip detector. It is shown that the use of coprocessing of the data received from both discriminators makes it possible to detect the cycle-slipping moments and introduce corrections for the slipping.     

GaAs MMIC for Handsetin Mobile Communication

Nanjing Electronic Devices Institute has fabricated Ga As MMICs for handset in mobilecommunication,include DPDTs,power amplifiers with switch,LNAs,and so on.TheMMICs operate at 90 0 MHz or 1 80 0 MHz,so the MMICs can be used in GSM handset orDCS1 80 0 handset.The DPDT can work on dual band.Front cover show the photo of thechip of power amplifiers with switch. Back cover show the photo of DPDTs. Typical specifi-cations are listed as follows:DPDT:Frequency/MHz:80 0～ 2 0 0 0…     

Jitter reduction of a digital phase-locked loop

This letter presents a jitter reduction technique for the digital phase-locked loop proposed by G. Pasternack and R. L. Whalin. In this technique, the lower N bits of load data from the first register are cut down and loaded into the final register as the round-off data. According to the experimental results, rounding off 5 bits in the second-order loop causes jitter to be reduced by 19.5 dB; therefore, this technique is useful for carrier tracking applications.     

GaAs pHEMT-based technology for microwave applications in a volume MMIC production environment on 150-mm wafers

The establishment of a 150-mm (6-in) gallium arsenide (GaAs) facility is described together with the development of very high yielding and cost-effective semiconductor device technologies and a manufacturing capacity of over 40000 wafers/annum. The background to the demand for very high volumes of RF products for this market is discussed, together with the prospects for future growth. The paper describes recent process development by the utilization of a data-driven yield management system to support the delivery of high-quality RF products to customers. Finally, "end of line" DC and RF testing of finished 150-mm GaAs pHEMT foundry wafers is described, enabling scalar measurements of power, noise, and intermodulation products as well as vector measurements of S-parameters and noise parameters at frequencies of up to 40 GHz.     

GaAs MMIC MESFET混频器性能比较

给出了几种 Ga As MESFET单片混频器结构与芯片测试结果比较。实验表明 ,在相同本振功率激励下 Ga As MMIC双栅混频器具有良好变频特性 ,栅混频器指标次之 ,漏混频器结构最简单 ,但变频特性不如前两种。另外 ,单片巴仑双平衡混频器具有高的动态范围和宽频段工作特点。     

移动通信用GaAs微波单片集成电路的CAD技术研究

介绍了一个移动通信用 Ga As MMIC集成电路 CAD系统。该系统包括单片电路器件模型系统和 CAD软件包。应用该系统已完成多个移动通信电路的优化设计 ,取得良好效果。     

一种低抖动电荷泵锁相环的设计

采用动态鉴频鉴相器、基于常数跨导轨到轨运算放大器的电荷泵、差分型环形压控振荡器,设计了一种低抖动的电荷泵锁相环。基于SMIC 0.18-μm CMOS工艺,利用Cadence软件完成了电路的设计与仿真。结果表明,动态的鉴频鉴相器,有效消除了死区。新型的电荷泵结构,在输出电压为0.5 V~1.5 V时将电流失配减小到了2%以下。压控振荡器在频率为1 MHz时输出的相位噪声为-94.87 dB在1 MHz,调谐范围为0.8 GHz~1.8 GHz。锁相环锁定后输出电压波动为2.45 mV,输出时钟的峰峰值抖动为12.5 ps。     

蓬勃发展的GaAs MMIC──1994 IEEE GaAs IC讨论会侧记

本文简要介绍了１９９４年ＧａＡｓＩＣ讨论会概况以及所展示的ＧａＡｓＭＭＩＣ的进展，并侧重于其应用领域的介绍。     

Gain-weighted technique for directly measuring loop bandwidth of split-loop phase-locked loop

A technique is described, for directly measuring the loop bandwidth of the recently proposed split-loop phase-locked receiver. This technique takes advantage of recent advances in laboratory test equipment, and is both rapid and straightforward. The characteristics produced permit the actual loop parameters to be determined, thus providing verification of the calculated performance.<>     

砷化镓单片微波集成电路工艺述评

本文讨论了砷化镓单片微波集成电路的优缺点、工艺特点、应用领域和今后展望.     

Chaos and bifurcation in a third-order digital phase-locked loop

Nonlinear dynamics of a third-order zero crossing digital phase locked loop (ZCDPLL) has been investigated. It has been observed that, while first and second-order ZCDPLLs show period doubling route to chaos, a third-order ZCDPLL manifests a disjoint periodic attractor in its route to chaos. Also, the complexity and predictability of the system dynamics have been characterized by using nonlinear dynamical measures such as Lyapunov exponent, Kaplan–York dimension, correlation dimension and Kolmogorov entropy. All the results show that the chaos in a third-order ZCDPLL is low dimensional.     

MMIC development for millimeter-wave space application

The latest millimeter-wave monolithic-microwave integrated-circuit (MMIC) developments and technologies at the Mitsubishi Electric Corporation, Kanagawa, Japan, concerning high power amplifiers, low-noise amplifiers and phase shifters have been summarized. It has been shown that high-efficiency, low-noise, and low-loss performance for millimeter-wave space applications can be achieved by employing pseudomorphic high electron-mobility transistor (p-HEMT) MMIC technology. The investigation for gamma-ray irradiation hardness has cleared that millimeter wave p-HEMT MMICs have over a 100 years of life against gamma-ray irradiation in the space environment     

An optimum phase-locked loop with a non-ideal filter

In communications engineering the problem of synchronization is vital. Any loss of synchronism is required to be restored in the shortest possible time. The concept of optimum PLL which utilizes a non-linear, memoryless feedback device was introduced by Ahmed and Cheng (1974). It was shown that this optimum PLL achieves synchronization in the minimum time if the filter were ideal.

This paper considers the optimization of the PLL with non-ideal filter. The input sinusoid and the VCO output are assumed to have the same frequency but to differ in phase. The object of this paper is to investigate whether the optimum PLL introduced earlier (Ahmed and Cheng, p. 254) still retains its virtues when the ideal filter is replaced by a non-ideal one.

The nonlinear Volterra integro-differential equation governing the PLL performance is solved by two different approaches and the solution indicates that the PLL in the presence of a non-ideal filter is optimal only within a certain range of variation of the parameter defining the non-linear device.     

Analytical derivation of a nonlinear FET-equivalent-circuit for MMIC applications

A new method for the derivation of a FET-equivalent-circuit is presented in this paper. The model which is valid at least in the frequency range of 45 MHz to 26.5 GHz allows a large-signal simulation of the FET. The elements of the equivalent-circuit are calculated analytically from the measured scattering parameters of the FET.     

Study of complete interconnect reliability for a GaAs MMIC power amplifier

By combining the finite element analysis (FEA) and artificial neural network (ANN) technique, the complete prediction of interconnect reliability for a monolithic microwave integrated circuit (MMIC) power amplifier (PA) at the both of direct current (DC) and alternating current (AC) operation conditions is achieved effectively in this article. As a example, a MMIC PA is modelled to study the electromigration failure of interconnect. This is the first time to study the interconnect reliability for an MMIC PA at the conditions of DC and AC operation simultaneously. By training the data from FEA, a high accuracy ANN model for PA reliability is constructed. Then, basing on the reliability database which is obtained from the ANN model, it can give important guidance for improving the reliability design for IC.