Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (V_GS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all V_GS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔV_th) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔV_th is generated by carrier trapping but not defect creation. It is also observed that the ΔV_th shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (N_T) and free carriers resulted in the increase of ΔV_th as the channel layer thickness increases.     

Degradation of n-channel a-Si:H/nc-Si:H bilayer thin-film transistors under DC electrical stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN_x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress (V_G = 25 V, V_D = 0), (ii) on-state bias stress (V_G = 25 V, V_D = 20 V) and (iii) off-state bias stress (V_G = −25 V, V_D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.     

Novel organic inverters with dual-gate pentacene thin-film transistor

We report on the fabrication and characterization of dual-gate pentacene organic thin-film transistors (OTFTs) with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ as a bottom-gate dielectric and PEALD 200 nm thick Al₂O₃ as a top-gate dielectric. The V_th of dual-gate OTFT has changed systematically with the application of voltage bias to top-gate electrode. When voltage bias from −10 V to 10 V is applied to top gate, V_th changes from 1.95 V to −9.8 V. Two novel types of the zero drive load logic inverter with dual-gate structure have been proposed and fabricated using PEALD Al₂O₃ gate dielectrics. Because the variation of V_th due to chemical degradation and the spatial variation of V_th are inherent in OTFTs, the compensation technology by dual-gate structure can be essential to OTFT applications.     

Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ_FE> 1 cm²V⁻¹s⁻¹) and excellent stability under gate bias stress (bias stress V_ds = 0V). However, after prolonged bias stress performed at high drain voltage, V_ds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V_ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.     

The influence of visible light on the gate bias instability of In-Ga-Zn-O thin film transistors

We investigated the effect of photon irradiation with various energies on the gate bias instability of indium-gallium-zinc oxide transistors. The illumination of red and green light on the transistor caused positive threshold voltage (V_th) shifts of 0.23 V and 0.18 V, respectively, while it did not affect the V_th value in blue light after a positive bias stress. However, the stability of transistors was deteriorated with increasing photon energy after a negative bias stress: negative V_th shifts for red (−0.23 V) and blue light (−3.7 V). This difference can be explained by the compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.     

A novel low temperature integration of hybrid CMOS devices on flexible substrates

In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm²/V s, respectively. Threshold voltages (V_t) are 1.14 V for nMOS and −1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Air‐Operable,High‐Mobility Organic Transistors with Semifluorinated Side Chains and Unsubstituted Naphthalenetetracarboxylic Diimide Cores: High Mobility and Environmental and Bias Stress Stability from the Perfluorooctylpropyl Side Chain

N,N′‐bis(3‐(perfluoroctyl)propyl)‐1,4,5,8‐naphthalenetetracarboxylic acid diimide (8–3‐NTCDI) was newly synthesized, as were related fluorooctylalkyl‐NTCDIs and alkyl‐NTCDIs. The 8–3‐NTCDI‐based organic thin‐film transistor (OTFT) on an octadecyltrimethoxysilane (OTS)‐treated Si/SiO₂ substrate shows apparent electron mobility approaching 0.7 cm² V^‐1s^‐1 in air. The fluorooctylethyl‐NTCDI (8–2‐NTCDI) and fluorooctylbutyl‐NTCDI (8–4‐NTCDI) had significantly inferior properties even though their chemical structures are only slightly different, and nonfluorinated decyl and undecyl NTCDIs did not operate predictably in air. From atomic force microscopy, the 8–3‐NTCDI active layer deposited with the substrate at 120 °C forms a polycrystalline film with grain sizes >4μm. Mobilities were stable in air for one week. After 100 days in air, the average mobility of three OTFTs decreased from 0.62 to 0.12 cm² V^‐1s^‐1, but stabilized thereafter. The threshold voltage (V_T) increased by 15 V in air, but only by 3 V under nitrogen, after one week. On/off ratios were stable in air throughout. We also investigated transistor stability to gate bias stress. The transistor on hexamethlydisilazane (HMDS) is more stable than that on OTS with mobility comparable to amorphous Si TFTs. V_T shifts caused by ON (30 V) and OFF (–20 V) gate bias stress for the HMDS samples for 1 hour were 1.79 V and 1.27 V under N₂, respectively, and relaxation times of 10⁶ and 10⁷ s were obtained using the stretched exponential model. These performances are promising for use in transparent display backplanes.     

ZnO Thin Film, Device, and Circuit Fabrication using Low-Temperature PECVD Processes

We report undoped ZnO films deposited at low temperature (200°C) using plasma-enhanced chemical vapor deposition (PECVD). ZnO thin-film transistors (TFTs) fabricated using ZnO and Al₂O₃ deposited in situ by PECVD with moderate gate leakage show a field-effect mobility of 10 cm²/V s, threshold voltage of 7.5 V, subthreshold slope <1 V/dec, and current on/off ratios >10⁴. Inverter circuits fabricated using these ZnO TFTs show peak gain magnitude (dV _out/dV _in) ~5. These devices appear to be strongly limited by interface states and reducing the gate leakage results in TFTs with lower mobility. For example, ZnO TFTs fabricated with low-leakage Al₂O₃ have mobility near 0.05 cm²/V s, and five-stage ring-oscillator integrated circuits fabricated using these TFTs have a 1.2 kHz oscillation frequency at 60 V, likely limited by interface states.     

Low-temperature and scalable complementary thin-film technology based on solution-processed metal oxide n-TFTs and pentacene p-TFTs

In this work, a completely scalable integration process is presented for organic–inorganic complementary logic, based on low-temperature spin-coated n-type metal oxide TFTs and thermally evaporated p-type pentacene TFTs. Both transistor types are photolithographically processed side-by-side, without the use of any shadow mask. High performance n-type metal oxide TFTs, post-annealed at a maximum temperature of only 250 °C, exhibit saturation mobilities exceeding 2 cm²/(V s), subthreshold swing as low as 0.19 V/decade and I_on/I_off ratios beyond 10⁷ after integration with p-type pentacene TFTs. Using this hybrid complementary technology, 5-stage and 19-stage ring-oscillators are demonstrated, operating at supply voltages as low as 2.5 V. The ring-oscillators oscillate at a frequency of more than 110 kHz, corresponding to stage delays as low as 0.74 μs, at a supply bias of 20 V.     

Multi-level non-volatile organic transistor-based memory using lithium-ion-encapsulated fullerene as a charge trapping layer

We report on multi-level non-volatile organic transistor-based memory using pentacene semiconductor and a lithium-ion-encapsulated fullerene (Li⁺@C₆₀) as a charge trapping layer. Memory organic field-effect transistors (OFETs) with a Si⁺⁺/SiO₂/Li⁺@C₆₀/Cytop/Pentacene/Cu structure exhibited a performance of p-type transistor with a threshold voltage (V_th) of −5.98 V and a mobility (μ) of 0.84 cm² V⁻¹ s⁻¹. The multi-level memory OFETs exhibited memory windows (ΔV_th) of approximate 10 V, 16 V, and 32 V, with a programming gate voltage of 150 V for 0.5 s, 5 s, and 50 s, and an erasing gate voltage of −150 V for 0.17 s, 1.7 s, and 17 s, respectively. Four logic states were clearly distinguishable in our multi-level memory, and its data could be programmed or erased many times. The multi-level memory effect in our OFETs is ascribed to the electron-trapping ability of the Li⁺@C₆₀ layer.     

Crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors

In this paper, we report on the fabrication of a crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors (TFTs). We used cyanoethylated pullulan (CEP) as a crosslinkable high-k polymer matrix and poly(ethylene-alt-maleic anhydride) (PEMA) as a polymeric crosslinking agent. Because PEMA has a high number of functional groups reactive to the hydroxyl groups of CEP, the use of PEMA is effective for minimizing the amount of remaining hydroxyl groups strongly related to the large current hysteresis and high off current of the organic TFTs. To investigate the potential of the CEP-PEMA mixture as a gate insulator, we fabricated 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C₈-BTBT) TFTs. The C₈-BTBT TFT with the 60 nm-thick CEP-PEMA gate insulator showed excellent TFT performance with a field-effect mobility of 1.4 cm²/V s and an on/off ratio of 2.4 × 10⁶.     

Photo-patternable polyimide gate insulator with fluorine groups for improving performance of 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiopene (C10-BTBT) thin-film transistors

Surface properties of gate insulators strongly affect the device performance of organic thin-film transistors (OTFTs). To improve the performance of OTFTs, we have developed photo-sensitive polyimide gate insulator with fluorine groups. The polyimide gate insulator film could be easily patterned by selective UV exposure without any photoinitiator. The polyimide gate insulator film, fabricated at 130 °C, has a dielectric constant of 2.8 at 10 kHz, and leakage current density of <1.6 × 10^?10 A/cm² while biased from 0 to 90 V. To investigate the potential of the polyimide with fluorine groups as a gate insulator, we fabricated C₁₀-BTBT TFTs. The field-effect mobility and the on/off current ratio of the TFTs were measured to be 0.76 ± 0.09 cm²/V s and >10⁶, respectively.     

High performance inkjet-printed C60 fullerene thin-film transistors: Toward a low-cost and reproducible solution process

We have demonstrated high performance inkjet-printed n-channel thin-film transistors (TFTs) using C₆₀ fullerene as a channel material. Highly uniform amorphous C₆₀ thin-film patterns were fabricated on a solution-wettable polymer gate dielectric layer by inkjet-printing and vacuum drying process. Fabricated C₆₀ TFTs shows great reproducibility and high performance; field-effect mobilities of 2.2–2.4 cm² V^?1 s^?1, threshold voltages of 0.4–0.6 V, subthreshold slopes of 0.11–0.16 V dec^?1 and current on/off ratio of 10⁷–10⁸ in a driving voltage of 5 V. This is due to the efficient annealing process that extracting the solvent residue and the formation of low trap-density gate dielectric surface.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Controllable threshold voltage of a pentacene field-effect transistor based on a double-dielectric structure

The authors report controllable threshold voltage (V_th) in a pentacene field-effect transistor based on a double-dielectric structure of poly(perfluoroalkenyl vinyl ether) (CYTOP) and SiO₂. When a positive switching voltage is applied to the gate electrode of the transistor, electrons traverse through the pentacene and CYTOP layers and subsequently trapped at the CYTOP/SiO₂ interface. The trapped electrons induce accumulation of additional holes in the pentacene conducting channel, resulting in a large V_th shift from ?4.4 to +4.6 V. By applying a negative switching voltage, the trapped electrons are removed from the CYTOP/SiO₂ interface, resulting in V_th returning to an initial value. The V_th shift caused by this floating gate-like effect is reversible and very time-stable allowing the transistor to be applicable to a nonvolatile memory that has excellent retention stability of stored data.     

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN_x/SiO₂ gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN_x/SiO₂) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (ΔV_TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.     

Enhanced electrical and photosensing properties of pentacene organic thin-film phototransistors by modifying the gate dielectric thickness

The effects of dielectric layer thickness on the electrical performance and photosensing properties of organic pentacene thin-film transistors have been investigated. To improve the electrical performance of pentacene thin-film transistors (TFTs), the poly-4-vinylphenol (PVP) polymer with various thicknesses was used in fabrication of the pentacene transistors. The pentacene thin-film transistor with the PVP dielectric layer of 70 nm exhibited a field-effect mobility of 4.46 cm²/Vs in the saturation region, a threshold voltage of −4.0 V, a gate voltage swing of 2.1 V/decade and an on/off current ratio of 5.1 × 10⁴. In the OFF-state, the photoresponse of the transistors increases linearly with illumination intensity. The pentacene transistor with the thinner dielectric layer thickness indicates the best photosensing behavior. It is evaluated that the electrical performance and photosensing properties of pentacene thin-film transistors can be improved by using various thickness dielectric layer.     

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N₂ anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO_x, the wet-N₂ anneal can greatly suppress the growth of unstable low-κ GeO_x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N₂ ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 10¹¹ eV⁻¹ cm⁻² and gate leakage current of 5.7 × 10⁻⁴ A/cm² at V_g = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N₂ ambient.