Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

p-type thin-film transistors with vacuum-deposited crystallized copper-doped germanium films

Copper-doped 10-nm-thick vacuum-deposited Ge films between vitreous aluminosilicate insulator films can be crystallized at 400°C, with hole mobilities of 80 cm²/V.s. They yield stable p-type TFT's with 10⁵on/off ratio which are process-compatible with n-type CdSe TFT's and thus usable for complementary on-board shift registers in active matrix displays.     

Self-aligned aluminum top-gate polysilicon thin-film transistorsfabricated using laser recrystallization and gas-immersion laser doping

We present electrical results from polysilicon thin film transistors (TFT's) fabricated using laser-recrystallized channels and gas-immersion laser-doped source-drain regions. A simple, four-level self-aligned aluminum top-gate process is developed to demonstrate the effectiveness of these laser processes in producing TFT's. The source-drain doping process results in source-drain sheet resistances well below 100 Ω/□. TFT field-effect mobilities in excess of 200 cm²/Vs are measured for the laser-fabricated unhydrogenated TFT's     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

Pentacene organic thin-film transistors-molecular ordering andmobility

Pentacene-based organic thin-film transistors (TFT's) with field-effect mobility as large as 0.7 cm²/V·s and on/off current ratio larger than 10⁸ have been fabricated. Pentacene films deposited by evaporation at elevated temperature at low-to-moderate deposition rates have a high degree of molecular ordering with micrometer-sized and larger dendritic grains. Such films yield TFT's with large mobility. Films deposited at low temperature or by flash evaporation have small grains and poor molecular ordering and yield TFT's with low mobility     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

The combined effects of low pressure NH3-annealing and H2 plasma hydrogenation on polysilicon thin-film transistors

The low pressure NH₃-annealing and the H₂ plasma hydrogenation were jointly used to improve the characteristics of polysilicon thin-film transistors (TFT's). It was found that the TFT's after applying the above treatments achieved better subthreshold swings, threshold voltages, field effect mobilities, off currents, and reliability. It is believed that the improvement was due to the gate oxynitride formation and the H₂-plasma had a better passivation effect on the oxynitride     

Characteristics of polysilicon thin-film transistor with thin-gatedielectric grown by electron cyclotron resonance nitrous oxide plasma

Polysilicon thin-film transistors (poly-Si TFT's) with thin-gate oxide grown by electron cyclotron resonance (ECR) nitrous oxide (N₂ O)-plasma oxidation is presented. ECR N₂O-plasma oxidation successfully incorporates nitrogen atoms at the SiO₂/poly-Si interface, consequently forms a nitrogen-rich layer with Si≡N bonds at a binding energy of 397.8 eV. ECR N₂ O-plasma oxide grown on poly-Si films shows higher breakdown fields than thermal oxide. The fabricated poly-Si TFT's with N₂ O-plasma oxide show better performance than those with ECR O₂ -plasma oxide, which results not only from the smooth interface but also oxygen- and nitrogen-plasma passivation     

XeCl Excimer laser annealing used in the fabrication of poly-Si TFT's

Mo-gate n-channel poly-Si thin-film transistors (TFT's) have been fabricated for the first time at a low processing temperature of 260°C. A 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate. TFT's were fabricated in the crystallized Si film. The channel mobility of the TFT was 180cm²/V.s when the a-Si:H was crystallized by annealing with a laser having an energy density of 200 mJ/cm². This result shows that high-speed silicon devices can be fabricated at a low temperature using XeCl excimer laser annealing.     

p-Channel TFT's using magnetron-sputtered Ta2O5films as gate insulators

Metal-gate thin-film transistors (TFT's) have been fabricated in layers of laser-recrystallized polycrystalline silicon on fused quartz substrates at processing temperatures below 625°C. Tantalum pentoxide (Ta2O5) was used as a gate insulator instead of a conventional thermally grown silicon dioxide (SiO2). Ta2O5gate insulator was deposited onto the recrystallized silicon layer at room temperature, using an RF-magnetron sputtering system. The reactive ion etching method, using CF4as a reactive gas, was employed in patterning deposited Ta2O5. These TFT's have exhibited p-channel depletion-mode characteristics with a threshold voltage of 2.5 V and a transconductance of 70 µS at Vg= - 2 V. An on-off current ratio exceeding 10⁵has been obtained.     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Optimization of silicon-germanium TFT's through the control ofamorphous precursor characteristics

Polycrystalline thin-film transistors (TFT's) are promising for use as high-performance pixel and integrated driver transistors for active matrix liquid crystal displays (AMLCD's). Silicon-germanium is a promising candidate for use as the channel material due to its low thermal budget requirements. The binary nature of the silicon-germanium system complicates the optimization of the channel deposition conditions. To date, little work has been done to perform this optimization, resulting in poor performance for SiGe TFT's. We report on optimization studies done on the low-pressure chemical vapor deposition of SiGe and its effect on TFT performance. We detail the results of a response surface characterization of SiGe deposition, and explain the obtained results in terms of atomistic models of deposition. Optimization strategies to enable the fabrication of high-performance SiGe TFT's are explained, Using these strategies, SiGe TFT's fabricated using solid phase crystallization and a 550°C process are demonstrated, with mobility greater than 40 cm²/V-s. Analysis is also performed on the effect of Ge-catalysis on the maximum optimization range. Results suggest that SiGe may offer enhanced optimization ranges over Si, as a result of this catalysis     

High-performance p-channel poly-Si TFT's using electron cyclotronresonance hydrogen plasma passivation

This letter presents a summary of the first detailed investigation of electron cyclotron resonance (ECR) hydrogen plasma exposure treatments of p-channel poly-Si thin film transistors (TFT's). It is shown that ECR hydrogenation can be much more efficient than RF hydrogenation. Poly-Si p-channel TFT's fabricated at low temperatures (⩽625°C) and passivated with the ECR hydrogenation treatment are shown to exhibit ON/OFF current ratios of 7.6×10⁷, subthreshold swings of 0.62 V/decade, threshold voltages of -4.6 V, and hole mobilities over 18 cm²/V.s     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Degradation due to electrical stress of poly-Si thin filmtransistors with various LDD lengths

The degradation phenomena of polycrystalline silicon (poly-Si) thin film transistors (TFT's) with various lightly-doped drain (LDD) length have been investigated. It is observed that the threshold voltage shift due to electrical stress varies with LDD length. The threshold voltage shift after 4 hours electrical stress of V_g=V_d =30 V in conventional, 0.5 μm, and 2 μm LDD poly-Si TFT's are about 2.7 V, 5.2 V, and 0.8 V, respectively