Photoreflectance study of electric field distributions in semiconductors heterostructures grown on semi-insulating substrates

We have studied the photoref lectance (PR) spectra from a MBE grown heterostructure consisting of 200 nm of Ga_0.83Al_0.17As, a 800 nm GaAs buffer layer on a semi-insulating (100) LEC GaAs substrate. By varying both the pump beam wavelength and modulation frequency (up to 100 kHz) we are able to identify the component layers, their quality and the properties of the various interfaces. In this study we find evidence for a low density of interface states between the GaAs buffer layer and GaAlAs layer and a relatively large density of interface states between the substrate and buffer regions. These states, previously observed by Deep Level Transient Spectroscopy of doped structures, are presumably associated with the interface produced by MBE growth on etched and air exposed substrates. However, in our material, since the substrate is semi-insulating and the buffer layer is undoped, it is difficult to resolve these states spatially by C-V techniques. Our results show that the PR technique can be used to characterize low conductivity or semi-insulating structures such as enhancement mode MESFET and HEMT type devices and it may be useful for the in-situ characterization of epigrown surfaces and interfaces     

Diffusion of zinc into gaas layers grown by molecular beam epitaxy at low substrate temperatures

We report the diffusion of zinc into low temperature (LT) GaAs grown by MBE at 200° C, the problems associated with using a silicon nitride film directly deposited on the LT GaAs as a Zn diffusion mask, and several schemes to avoid the problems. The Zn diffusion coefficient is measured (sealed-ampoule technique) to be about one order of magnitude higher in the LT GaAs than in normal GaAs, attributed to a large quantity of defects including arsenic antisites (As_Ga) in the LT GaAs. The effectiveness of silicon nitride as a Zn diffusion mask depends if the mask is deposited directly on the LT GaAs. The failure of the nitride directly deposited on the LT GaAs to stop the Zn is attributed to arsenic atoms outdiffusing from the As-rich LT GaAs (about 1 at. % excess As) into the nitride. Several structures are introduced including a 100-Å thick GaAs layer on the LT GaAs that are effective in preserving the diffusion mask properties of the silicon nitride.     

Diode structures from amorphous low-temperature GaAs

The effect of annealing on the electrical properties of a GaAs diode structure, which incorporated a nominally undoped low-temperature (LT) layer on top of conventionally grown p-type GaAs, is examined. Unannealed GaAs grown by molecular beam epitaxy at substrate temperatures below 250°C is amorphous and highly resistive. Annealing at high temperatures converts the undoped LT-GaAs from amorphous to single crystal material. The annealed material is n-type. The current-voltage characteristics of the LT on p-type GaAs structures showed greater asymmetry, with lower reverse leakage currents, as the anneal temperature was increased above 400°C. This reflects the improved crystal quality of the LT layer.     

Effects of a buffer layer on free-carrier depletion in n-type GaAs

The authors develop a simple model for the effects of a buffer layer on free-carrier depletion from a conductive semiconductor layer. Poisson's equation is solved in the depletion approximation to give an expression for the sheet free-carrier charge transferred from a conductive semiconductor layer to acceptor (or donor) states at interfaces or in the bulk material. The principal goal is to show that a relatively thin, undoped buffer layer between the substrate and active layer can dramatically lower the free-carrier loss to substrate interface states. Data on molecular-beam epitaxial, n-type GaAs agrees well with the theory, but show that there still is some loss at the interface between the active layer and buffer layer     

Dislocation-Induced deep level states in In0.08Ga0.92As/GaAs heterostructures

We have performed luminescence experiments on In_0.08Ga_0.92As/GaAs heterointerfaces to explore the energy distribution of deep level states in the bandgap for two cases: (1) unrelaxed, pseudomorphic In_0.08Ga_0.92As films (200Å thick), which have few if any dislocations at the interface, and (2) partially relaxed In_0.08Ga_0.92As films (1000Å thick) which are expected to have a substantial interfacial dislocation density. A combined photoluminescence and cathodoluminescence technique is used which allows us to profile the sample luminescence through the buried interface region. Our results show the existence of deep level luminescent features characteristic of the GaAs substrate and features common to In_0.08Ga_0.92As and GaAs, as well as the existence of a deep level feature near 1 eV photon energy which undergoes a shift in energy depending upon the degree of strain relaxation in the In_0.08Ga_0.92As film. In addition, a deep level feature near 0.83 eV becomes prominent only in In_0.08Ga_0.92As films which have relaxed, and thus contain misfit dislocations at the interface. These deep level differences may be due to bandgap states associated with the intrinsic dislocation structure, impurities segregated at the dislocation, or bulk point defects, or threading dislocations generated during the strain relaxation. Previous work has determined that a deep level state 0.7 eV above the valence band edge would account for the electrical behavior of relaxed In_0.08Ga_0.92As/GaAs interfaces, which is in good agreement with the range of deep level transitions near 0.8 eV photon energy which we observe. These measurements suggest that photo- and cathodoluminescence measurements of deep level emission in these III-V semiconductors can provide a useful indicator of electrically active defect densities associated with misfit dislocations.     

GaAs超高速电压比较器及利用低温MBE GaAs缓冲层的改进设计

简要介绍了ＧａＡｓ超高速电压比较器的国内外发展水平。设计并研制了具有１．０ＧＨｚ时钟频率的高性能电压比较器。该器件采用亚微米ＧａＡｓＭＥＳＦＥＴ工艺技术，其电压分辨率高达１１．３ｍＶ，功耗仅为２７４ｍｗ。最后给出了利用低温分子束外延生长ＧａＡｓ作缓冲层的进一步改进设计。     

Sharp line emission spectra from GaAs FET like structures

Magneto-optical analysis of prominent photoluminescence lines from GaAs FET structures has been performed. Fifteen samples were investigated. Each consisted of a sulfur doped active layer on a high resistivity buffer layer (both epitaxially grown films) on a chromium doped GaAs substrate. The active layers were generally 2μm thick or less, except for two thicker layers (4 and 5μm) grown especially for this study. Buffer layer thicknesses ranged from 1.5 to 26μm. A model based on carrier diffusion through the active layer has been used to interpret the spectra as originating from the active-buffer interface region. All spectra contain strong-evidence of two donorbound exciton complexes associated with sulfur (1.51417eV) and silicon (1.51412eV). Other sharp spectral features included up to six lines associated with more complicated complexes. Linear Zeeman and quadratic diamagnetic behavior of the lines in applied magnetic fields are discussed. Supported under AF Contract F33615-77-C-5003 Supported under AF Contract F33615-76-C-1207     

High purity and chrome-doped GaAs buffer layers grown by liquid phase epitaxy for mesfet application

High purity GaAs buffer layers of carrier concentration in the low (l-5)×l0^l4/cm³ range with 77K electron mobility over 100,000 cm²/V-sec and 300K mobility around 8000 cm?/ V-sec have been grown by liquid phase epitaxy on Cr-doped GaAs substrates using the graphite sliding boat method. The high purity has been achieved with systematic and concurrent long term bake-outs (24 hrs) of both LPE melt and substrate, both exposed to the H₂ ambient gas stream at 775?C, prior to epitaxial growth at 700?C. Substrate surface degradation was reduced by using Ga:GaAs etch melts that were undersaturated at 700?C by 5? to 40?C. Best buffer layer morphologies with regard to surface planarity were obtained using etch melts that were saturated by near 85% of weight of GaAs at 700°C. The importance of substrate preconditioning in order to achieve the low ( 1 -2)×l0¹⁴ was examined and found to be critical. Melt and substrate bake outs at 800?C, and use of a 40?C undersaturated etch melt prior to epitaxial growth at 800?C resulted in a p-type layer of carrier concentration, 1 .9×l0^l2/cm³ and resistivity 1×10⁵ ohm-cm. Chromium doping at 700?C resulted in buffer layers with sheet resistivities greater than 10 ohms/sq and low pinhole densities.     

Band-bending effect of low temperature GaAs on a pseudomorphic modulation-doped field-effect transistor

Low temperature photoluminescence (PL) measurements on pseudomorphic modulation-doped transistors with a low-temperature (LT) GaAs layer in the GaAs buffer layer clearly show a decrease in the quantum well PL transition energies compared to a structure with no LT GaAs. Self-consistent calculations of the electron and hole bandstructure suggest that the observed increase in the redshift in PL energies with increasing quantum well-LT GaAs spacing can be attributed to band bending induced by the Fermi level pinning at the undoped GaAs/LT GaAs interface and a novel carrier compensation effect of LT GaAs.     

Performance of power FET's fabricated on MBE-Grown GaAs layers

Power GaAs FET's of various sizes have been fabricated using MBE material containing a 1 µm-thick semi-insulating buffer layer. These devices, when operated between 6 and 12 GHz, exhibited state-of-the-art microwave performance. For example, the 3 mm devices gave an output power of 1.5 W with 10.9 dB associated gain at 6.4 GHz, a power-added efficiency of 42.6% with 1.4 W output power and 6.4 dB associated gain at 8 GHz. The results confirm the capability of MBE for producing high quality material with a sharp active layer/buffer interface.     

Hg1—xCdxTe多层薄膜材料结构缺陷的透射电子显微镜测定

用透射电镜对Ｈｇ１－ｘＣｄＴｅ／ＣｄＴｅ和ＣｄＴｅ／ＧａＡｓ两种异质结的横截面进行了观测分析，对异质结附近的某些结构缺陷，如微孪晶的尺寸，几何形态、层错、界面失配位错的组态特征进行了研究，并对多层膜之间的取向差进行了分析，说明在ＧａＡｓ衬底上用分子束外延法制备的Ｈｇ１－ｘＣｄｘＴｅ／ＣｄＴｅ／ＧａＡｓ多层膜，就大量结构缺陷而言，ＣｄＴｅ缓冲层对Ｈｇ１－ｘＣｄｘＴｅ外延层起到了屏障作用，在Ｈｇ１－ｘ     

PHEM T 材料MBE 生长及其应用

我们对PHEMT材料中应变沟道InGaAs层生长条件进行了优化,并采用了LT-GaAs中缺陷扩散的阻挡层.功率PHEMT器件结果为在栅长Lg=1.0μ时,跨导g\-m≥400 ms/mm,BV\-\{DS\}>1 5V,BV\-\{GS\}>10V表明该材料有较好的性能.作为材料的缓冲层,结果表明器件性能优良 ,是国内最好结果.     

Znse/GaAs超晶格的电子态和芯态激子

本文用半经验紧束缚法计算了ZnSe/GaAs(001)超晶格的能带结构,研究了其能隙与有效质量随层厚的变化.计算了(ZnSe)_5/(GaAs)_5超晶格中与杂质有关的芯态激子,其结果能说明相应异质结中束缚在Ga上的激子峰.本文还提出了该材料中导带底存在界面态.     

Depth defined optoelectronic modulation spectroscopy

It is shown that if the gate depletion region of a MESFET is maintained with a constant width, channel current optoelectronic modulation spectroscopy reveals a spectrum of responses arising predominantly from charge variations in the depletion region at the interface between the active layer and the substrate. Optically induced charge variations as small as 2 × 10⁹ electrons/cm²/eV have been detected. A refinement of the basic method is described which should allow the responses of electron states in a region of selected depth within the active layer states to be seen. The method will be of particular value in observing states that have a role in back-gating.     

Defect state assisted tunneling in intermediate temperature molecular beam epitaxy grown GaAs

Current transport in molecular beam epitaxy (MBE) GaAs grown at low and intermediate growth temperatures is strongly affected by defects. A model is developed here that shows that tunneling assisted by defect states can dominate, at some bias ranges, current transport in Schottky contacts to unannealed GaAs material grown at the intermediate temperature range of about 400°C. The deep defect states are modeled by quantum wells which trap electrons emitted from the cathode before re-emission to semiconductor. Comparison of theory with experimental data shows defect states of energies about 0.5 eVbelow conduction band to provide the best fit to data. This suggests that arsenic interstitials are likely to mediate this conduction. Comparison is also made between as-grown material and GaAs grown at the same temperature but annealed at 600°C. It is suggested that reduction of these defects by thermal annealing can explain lower current conduction at high biases in the annealed device as well as higher current conduction at low biases due to higher lifetime. Quenching of current by light in the as-grown material can also be explained based on occupancy of trap states. Identification of this mechanism can lead to its utilization in making ohmic contacts, or its elimination by growing tunneling barrier layers.     

A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure, a 0.8-μm Si_0.1 Ge_0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si_0.1Ge_0.9 layer. A 0.8-μm Si_0.05Ge_0.95 layer and a 1-μm top Ge layer were subsequently grown. The strained Si_0.05Ge_0.95/Si_0.1Ge_0.9 and Ge/Si_0.05Ge_0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1–3-μm GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600°C. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 μm (2.6-μm SiGe-buffer structure +2.5-μm GaAs layer).     

A comparison of the critical thickness for MBE grown Lt-GaAs determined by In-Situ ellipsometry and transmission electron microscopy

The growth of low temperature (LT) GaAs by molecular beam epitaxy has been studied using ellipsometry. Different regimes of growth were observed in the data, depending on film thickness. Epitaxial growth of pseudomorphic LT-GaAs occurred immediately above the substrate, followed by a layer with changing dielectric properties. This upper layer can be modeled as a two-phase region consisting of epitaxial LT-GaAs and small grained, polycrystalline GaAs, which increases in volume fraction with increasing layer thickness. For sufficiently thick LT layers, cross-sectional transmission electron microscopy analysis showed pyramidal defects that were composed primarily of highly twinned regions. The ellipsometry data showed a deviation from the homogeneous growth model at a thickness less than the thickness at which the pyramidal defects nucleated in all samples.     

Nitride-based MQW LEDs with multiple GaN-SiN nucleation layers

Nitride-based light emitting diodes (LEDs) separately prepared with a conventional single low-temperature (LT) GaN nucleation layer and multiple GaN-SiN nucleation layers were both prepared. It was found that we could reduce defect density and thus improve crystal quality of the GaN-based LEDs by using multiple GaN-SiN nucleation layers. With a 20-V applied reverse bias, it was found that the reverse leakage currents measured from the LED with a single LT GaN nucleation layer and the one with 10-pair GaN-SiN nucleation layers were 1.5/spl times/10/sup -4/ and 2.5/spl times/10/sup -6/ A, respectively. It was also determined that we could use the multiple GaN-SiN nucleation layers to enhance the output intensity of near ultraviolet (UV) LEDs and to improve the reliability of nitride-based LEDs.     

ALE法对InSb/GaAs异质薄膜电学性能的改进

以GaAs(100)为衬底,采用原子层外延(ALE)的方法在GaAs缓冲层和常规InSb外延层间引入85个周期约30 nm的InSb低温缓冲层,以快速降低InSb和GaAs界面间较大的晶格失配(14.6%)对外延层质量造成的不利影响,从而改进异质外延薄膜的电学性能。实验结果显示,ALE低温缓冲层能较快地释放晶格失配应力,降低位错密度。室温和77 K的Hall测试显示,引入低温ALE缓冲层生长的InSb/GaAs异质外延薄膜,其InSb外延层本征载流子浓度和迁移率等电学性能较常规的方法有着较大的改进。     

Effects of GaAs buffer layer and lattice-matching on deep levels in Zn(S)Se/GaAs heterostructures

The effects of GaAs buffer layer and lattice-matching on the nature of deep levels involved in Zn(S)Se/GaAs heterostructures are investigated by means of deeplevel transient spectroscopy (DLTS). The heterojunction diodes (HDs) where nZn(S)Se is grown on p⁺-GaAs by metalorganic vapor phase epitaxy are used as a test structure. The DLTS measurement reveals that when ZnSe is directly grown on a GaAs substrate, there exist five electron traps A-E at activation energies of 0.20, 0.23, 0.25, 0.37, and 0.53 eV, respectively. Either GaAs buffer layer and lattice-matching may reduce the incorporation of traps C, D, and E, implying that these traps are ascribed to surface treatment of GaAs substrate and to lattice relaxation. Concentration of trap B, which is the most dominant level, is proportional to the donor concentration. However, in the ZnSSe/GaAs sub. HD, another trap level, instead of trap B, locates at the almost same position as that of trap B, and it shows anomalous behavior that the DLTS peak amplitude changes drastically as changing the rate windows. This is explained by the defect generation through the interaction between sulfide and a GaAs substrate surface. For the trap A, the concentration is a function of donor concentration and lattice mismatch, and the origin is attributed to a complex of donor induced defects and dislocations.