A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-$mu$m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5–6.2 dB with bandwidth of 3.1–10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is ${-} $11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.      

A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

A Low-Power Self-Forward-Body-Bias CMOS LNA for 3–6.5-GHz UWB Receivers

A low-power low-noise amplifier (LNA) implemented in 0.18 $mu$m CMOS technology utilizing a self-forward-body-bias (SFBB) technique is proposed for UWB low-frequency band system. By using the SFBB technique, it reduces supply voltage as well as saves additional bias circuits, which leads to low power consumption of 4.5 mW with low supply voltage of 1.06 V for two drain-to-source voltage drops. The complementary architecture and direct coupling technique between the first two stages also save bias circuits. The measurement result shows that the proposed LNA presents a maximum power gain of 16 dB with a good input impedance matching (${rm S}11 < - 12$ dB) and an average noise figure of 2.65 dB in the frequency range of 3–6.5 GHz.      

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

A BiCMOS Ultra-Wideband 3.1–10.6-GHz Front-End

This paper presents a direct-conversion receiver for FCC-compliant ultra-wideband (UWB) Gaussian-shaped pulses that are transmitted in one of fourteen 500-MHz-wide channels within the 3.1–10.6-GHz band. The receiver is fabricated in 0.18-$mu$m SiGe BiCMOS. The packaged chip consists of an unmatched wideband low-noise amplifier (LNA), filter, phase-splitter, 5-GHz ISM band switchable notch filter, 3.1–10.6-GHz local oscillator (LO) amplifiers, mixers, and baseband channel-select filters/buffers. The required quadrature single-ended LO signals are generated externally. The average conversion gain and input$P_1 dB$are 32 dB and$-$41 dBm, respectively. The unmatched LNA provides a system noise figure of 3.3 to 5 dB over the entire band. The chip draws 30 mA from 1.8 V. To verify the unmatched LNA's performance in a complete system, wireless testing of the front-end embedded in a full receiver at 100 Mbps reveals a$10^-3$bit-error rate (BER) at$-$80 dBm sensitivity. The notch filter suppresses out-of-band interferers and reduces the effects of intermodulation products that appear in the baseband. BER improvements of an order of magnitude and greater are demonstrated with the filter.     

Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners

This paper presents an electrostatic discharge (ESD)- protected ultra-wideband (UWB) low-noise amplifier (LNA) for full-band (170-to-1700 MHz) mobile TV tuners. It features a PMOS-based open-source input structure to optimize the I/O swings under a mixed-voltage ESD protection while offering an inductorless broadband input impedance match. The amplification core exploiting double current reuse and single-stage thermal-noise cancellation enhances the gain and noise performances with high power efficiency. Optimized in a 90-nm 1.2/2.5-V CMOS process with practical issues taken into account, the LNA using a constant- $g _{m}$ bias circuit achieves competitive and robust performances over process, voltage and temperature variation. The simulated voltage gain is 20.6 dB, noise figure is 2.4 to 2.7 dB, and IIP3 is $+10.8~hbox{dBm}$ . The power consumption is 9.6 mW at 1.2 V. $vert {rm S} _{11} vert ≪ -10~{hbox {dB}}$ is achieved up to 1.9 GHz without needing any external resonant network. Human Body Model ESD zapping tests of $pm 4~{hbox {kV}}$ at the input pins cause no failure of any device.      

3.1～5.2GHz超宽带可变增益低噪声放大器设计

低噪声放大器是超宽带接收机系统中最重要的模块之一,设计了一种可应用于3.1～5.2GHz频段超宽带可变增益低噪声放大器。电路输入级采用共栅结构实现超宽带输入匹配,并引入电流舵结构实现了放大器的可变增益。仿真基于TSMC 0.18μm RF CMOS工艺。结果表明,在全频段电路的最大功率增益为10.5dB,增益平坦度小于0.5dB,噪声系数小于5dB,输入反射系数低于-15dB,在1.8V电源电压下,功耗为9mW。因此,该电路能够在低功耗超宽带射频接收机系统中应用。     

低功耗IR-UWB接收机和LNA设计研究

在分析各种超宽带(UWB)接收机系统结构的基础上,提出了一种低功耗IR-UWB接收机结构.该结构基于非相干通信机制,使用自混频技术和脉冲宽度调制方式(PPM).在该结构中,低噪声放大器(LNA)的低功耗优化是系统低功耗实现的关键.综合分析各种宽带LNA结构,提出了一种低功耗LNA设计.该LNA采用65 nmCMOS标准...     

A Low-Power Linear SiGe BiCMOS Low-Noise Amplifier for Millimeter-Wave Active Imaging

This letter presents a low-power linear and wideband two-stage millimeter-wave low-noise amplifier (LNA) fabricated in a low-cost 0.18 $mu{rm m}$ SiGe BiCMOS technology. Design techniques utilized to optimize the gain and NF and to achieve high linearity and wideband at W-band are addressed. The LNA achieves a peak power gain of 14.5 dB at 77 GHz with a 3 dB bandwidth of 14.5 GHz from 69 to 83.5 GHz. The measured NF is 6.9 dB at 77 GHz and is lower than 8 dB from 64 to 81 GHz. Both input and output return losses are better than 11 dB and 17 dB at 77 GHz, respectively. The measured input 1 dB compression point is $-$11.4 dBm at 77 GHz with low power consumption of only 37 mW.      

Design of a capacitor cross-coupled dual-band LNA with switched current-reuse technique

This paper presents the design of a 2.5/3.5-GHz dual-band low-power and low-noise CMOS amplifier (LNA), which uses the capacitor cross-coupling technique and current-reuse method with four switches. The proposed LNA uses a single RF block and a broadband input stage, which is a key aspect for the easy reconfiguration of a dual-band LNA. Switching at the inter-stage and output allows for the selection of a different standard. The dual-band LNA attenuates the undesired interference of a broadband gain response circuit, which allows the linearity of the amplifier to be improved. The capacitor cross-coupled gm-boosting method improves the NF and reduces the current consumption. The proposed LNA employs a current-reused structure to decrease the total power consumption. The inter-stage and output switched resonators switch the LNA between the 2.5-GHz and 3.5-GHz bands. The proposed dual-band LNA optimises power consumption by the securing gain, noise figure and linearity. The simulated performance reveals gains of 16.7 dB and 19.6 dB, and noise figures of 3.04 dB and 2.63 dB at the two frequency bands, respectively. The linearity parameters of IIP3 are ?5.7 dBm at 2.5 GHz and ?9.7 dBm at 3.5 GHz. The proposed dual-band LNA consumes 5.6 mW from a 1.8 V power supply.     

A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers

A fully integrated differential low-power low-noise amplifier (LNA) for ultrawideband (UWB) systems operating in the 3-5-GHz frequency range is presented. A two-section LC ladder input network is exploited to achieve excellent input match in a wideband fashion and to optimize the noise performance. Prototypes fabricated in a digital 0.13-/spl mu/m complementary metal oxide semiconductor technology show the following performance: 9.5-dB peak power gain, 3.5-dB minimum noise figure, -6-dBm input-referred 1-dB compression point, and -0.8-dBm input-referred third-order intercept point, while drawing 11mA from a 1.5-V supply. The realized LNA is compared with previously reported LNAs tailored for the same frequency range.     

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$mu{hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, $LC$ ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-$mu{hbox{m}}$ CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.      

A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS

In this letter, a 0.1–20 GHz low-power low noise amplifier (LNA) is presented. A novel self-biased resistive- feedback topology is proposed. Two inductors inside the feedback loop and a shunt-peaking inductor are exploited to extend the bandwidth. A PMOSFET with inductive degeneration is chosen as the load to boost the gain while maintaining low noise figure (NF) at high frequencies. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability over the entire bandwidth. All inductors are small due to the presence of feedback. The LNA was fabricated using a digital 90 nm CMOS process with 12.7 dB peak power gain, 3.3 dB minimum NF, and ${- 1}~{rm dBm}$ peak input-referred third-order intercept point (IIP3). With 12.6 mW power consumption and 0.12 ${rm mm}^{2}$ active area, this wideband LNA may replace distributed amplifiers (DAs) in many applications.      

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

Gain-Enhancement Techniques for CMOS Folded Cascode LNAs at Low-Voltage Operations

In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, a $G_{m}$-boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-$mu{hbox {m}}$ CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured $P_{{rm in}-1 {rm {dB}}}$ and ${rm IIP}_{3}$ are $-$18 and $-$ 8.6 dBm, respectively. For the LNA with a $G_{m}$-boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW.      

High-Voltage-Gain CMOS LNA For 6–8.5-GHz UWB Receivers

The design of a fully integrated CMOS low noise amplifiers (LNA) for ultra-wide-band (UWB) integrated receivers is presented. An original LC input matching cell architecture enables fractional bandwidths of about 25%, with practical values, that match the new ECC 6–8.5-GHz UWB frequency band. An associated design method which allows low noise figure and high voltage gain is also presented. Measurements results on an LNA prototype fabricated in a 0.13- $mu$m standard CMOS process show average voltage gain and noise figure of 29.5 and 4.5 dB, respectively.      

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A 0.18-$muhbox m$CMOS Selective Receiver Front-End for UWB Applications

This paper addresses the problem of 5–6-GHz WLAN interferer rejection in a direct-conversion receiver front-end for multi-band orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) applications. The IC, realized in a 0.18-$muhbox m$CMOS technology, comprises a single-ended voltage–voltage feedback low-noise amplifier (LNA) and a quadrature mixer. The LNA employs a double-peak single-notch network in the output load, amplifying UWB groups #1 and #3, while rejecting WLAN interferes in the 5–6-GHz frequency range. The mixer, based on a merged quadrature topology, also realizes a second-order low-pass filtering. Fabricated dies have been bonded on PCB for characterization. The front-end, drawing 10 mA from 1.8 V, achieves a 1-dB gain desensitization with a$-$6.5-dBm interferer power at 5.5 GHz. Other measured performances are 5.2-dB and 7.7-dB minimum and maximum noise figure (NF),$-$3.5-dBm minimum IIP3 and$+$34.5-dBm minimum in-band IIP2 and$+$21-dBm out-of-band IIP2.     

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain \(\hbox {S}_{21}\) of \(20.10 \pm 1.65\,\hbox {dB}\) across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, \(\hbox {S}_{11}\), lies below \(-\,10\) dB from 4.9–9.1 GHz frequency. Moreover, the output reflection (\(\hbox {S}_{22}\)) and reverse isolation (\(\hbox {S}_{12}\)), is below \(-\,10\) and \(-\,48\) dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure (\(\hbox {NF}_{min}\)) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of \(\pm \,0.45\,\hbox {dB}\) in its \(\hbox {NF}_{min}\) characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is \(-\,4.22\) dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of \(\pm \,115\,\hbox {ps}\) and \(\pm \,1.65\,\hbox {dB}\), respectively.