An optimised dynamic bottleneck dispatching policy for semiconductor wafer fabrication

A dynamic bottleneck dispatching (DBD) policy is designed in this paper to detect bottlenecks in a timely way and make adaptive dispatching decisions of semiconductor wafer fabrication systems according to the real-time conditions. Control parameters of the proposed DBD algorithm are optimised by response surface methodology (RSM) and desirability functions. Numerical results show that DBD outperforms common scheduling rules such as CR?+?FIFO, EDD, SRPT, SPT, SPNB and an existing dynamic bottleneck dispatching method.     

Integer programming-based real-time dispatching (i-RTD) heuristic for wet-etch station at wafer fabrication

A real-time dispatching heuristic derived from an optimal binary integer programming model (i-RTD) to minimise the makespan of the automatic wet-etch station (AWS) scheduling problem with a chemical draining constraint is presented. Each chemical bath is drained and refilled every several days. This draining process, known as chemical dumping in the industry, occurs during the middle of a process and interrupts production. This chemical draining event creates a need for intelligent flow shop scheduling so that all baths are optimally utilised and so that jobs can skip a bath being drained and move to the next bath without interruption. The production losses from these interruptions can be minimised by optimally sequencing jobs before they enter the AWS. This paper first creates the binary integer programming (BIP) model to exactly describe the AWS scheduling problem, which later forms the basis for the i-RTD model to generate an efficient solution in real time. This unique heuristic accounts for the chemical draining constraint, time window constraint, zero wait constraint, and real-time constraint and represents a new dispatching paradigm of considerable practical interest.     

Selection of dispatching rules on multiple dispatching decision points in real-time scheduling of a semiconductor wafer fabrication system

Semiconductor wafer fabrication involves one of the most complex manufacturing processes ever used. To control such complex systems, it is a challenge to determine appropriate dispatching strategies under various system conditions. Dispatching strategies are classified into two categories: a vehicle-initiated dispatching policy and a machine-initiated dispatching policy. Both policies are important to improve the system performance, especially for the real time control of the system. However, there has been little research focusing on combining them under various situations for the semiconductor manufacturing system. In addition, it is shown that no single dispatching strategy consistently dominates others in all situations. Therefore, the goal of this study is to develop a scheduler for selection of dispatching rules for dispatching decision variables in order to obtain the desired performance measures given by a user for each production interval. For the proposed methodology, simulation and competitive neural network approaches are used. The results of the study indicate that applying our methodology to obtaining a dispatching strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.     

Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities

In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be used to answer important managerial questions for effective management of the semiconductor wafer fabrication process.     

Capacity requirements planning for twin Fabs of wafer fabrication

Based on the assumption of infinite capacity, a Capacity Requirements Planning System (CRPS) is developed for twin fabs of wafer fabrication. Several shared equipments exist only in one of the twin fabs linked by an Inter-Fab Material Handling System. CRPS consists of four major modules. WIP-Pulling Module pulls work-in-process (WIP) that is the closest to the end of the process route to meet the Master Production Schedule. Workload Accumulation Module then calculates the expected equipment loading in different time buckets. If WIP cannot meet the Master Production Schedule (MPS) requirement, new wafer lots need to be released. Wafer Release Time Module is used to determine the release time of new lots by evaluating their expected equipment loading at the twin fabs on various time buckets. According to the lot release time, Wafer Start Fab Module can be used to evaluate the expected loading for each of the twin fabs and determine the start fab to optimise the workload balance among these twin fabs on various days. Based on experimental design, simulation results show that CRPS can balance the equipment loading between the twin fabs with shared equipment, on various days, and across various equipments at various levels of demands.     

A practical fab design procedure for wafer fabrication plants

Facility design is crucial to the performance of wafer fabs in the semiconductor industry. This research proposes a practical Fab Design Procedure (FDP) to conduct quick calculations to develop and evaluate initial fab design alternatives. A series of practical formulae are presented to sequentially determine the following design parameters from an interbay point of view: the required number of machines; machine grouping and allocation; interbay flow matrix; bay dimension and location; interbay distance matrix; the required number of vehicles in an interbay material handling system; and the average wafer moving distance. Rules-of-thumb for wafer fab design on the basis of FDP are also suggested. A case study is used to demonstrate the effectiveness and efficiency of FDP. Results indicate that FDP is able to quickly calculate the required number of machines and related fab design parameters. With this tool, fab designers would be able to evaluate design alternatives and conduct what-if analysis in the initial phase of fab design.     

Cycle time-oriented mid-term production planning for semiconductor wafer fabrication

Wafers are produced in an environment with uncertain demand and failure-prone machines. Production planners have to react to changes of both machine availability and target output, and revise plans appropriately. The scientific community mostly proposes WIP-oriented mid-term production planning to solve this problem. In such approaches, production is planned by defining targets for throughput rates and buffer levels of selected operations. In industrial practice, however, cycle time-oriented planning is often preferred over WIP-oriented planning. We therefore propose a new linear programming formulation, which facilitates cycle time-oriented mid-term production planning in wafer fabrication. This approach plans production by defining release quantities and target cycle times up to selected operations. It allows a seamless integration with the subordinate scheduling level. Here, least slack first scheduling translates target cycle times into lot priorities. We evaluate our new methodology in a comprehensive simulation study. The results suggest that cycle time-oriented mid-term production planning can both increase service level and reduce cycle time compared to WIP-oriented planning. Further, it requires less modelling effort and generates plans, which are easier to comprehend by human planners.     

Finite-capacity production planning algorithms for a semiconductor wafer fabrication facility

We consider the problem of production planning for a semiconductor wafer fabrication facility producing application-specific integrated circuits (ASICS) to customer order. Using a simple planning algorithm based on forward scheduling for WIP and backward scheduling for new orders, the effects of the level of detail at which the production process is modelled was examined. A simulation study showed that considering all near-constraint workcentres explicitly as having finite-capacity gives the best results. Also examined were the effects of undercapacity planning, and it was shown that when coupled with a shop-floor scheduling procedure driven by the planned completion date rather than customer due dates, significant improvements in both delivery performance and system predictability were obtained.     

Shift scheduling for steppers in the semiconductor wafer fabrication process

In this paper, an approach is proposed for scheduling stepper machines that are acting as bottleneck machines in the semiconductor wafer fabrication process. We consider the problem of scheduling the steppers for an 8 hour shift, determining which types of wafer lots to work on each machine. The scheduling objective is to find the optimal stepper allocations such that the schedule meets target production quantities that have been derived from the given target Work-In-Process (WIP) levels. A Mixed Integer Programming (MIP) model is formulated, and three heuristic approaches are proposed and tested to approximately solve the M1P model. Numerical tests show that one of the proposed heuristics using linear programming relaxation of MIP generates, on average, schedules within 5° of the optimum values.     

A neural network approach for batching decisions in wafer fabrication

This paper considers a stochastic batching problem for a batch process in wafer fabrication, where various numbers of wafer lots are allowed to process together in each batch, and wafer lots arrive randomly but not in a specified pattern. The objective is to determine the optimal size (number of wafer lots) of each batch with respect to the measure of minimizing the mean queueing time of wafer lots. For the problem, a multi-layer perceptron neural network model is proposed to make real-time batching control, and its effectiveness is investigated in comparison with that of the well-known minimum batch size policy.     

Investigation of flow mechanisms in semiconductor wafer fabrication

The semiconductor wafer fabrication manufacturing environment is one of the most difficult in which to plan and control. Long and re-entrant routings and high yield loss on new products are two characteristics that impact system performance. This research provides an exploratory investigation of two simplified flow control mechanisms to determine if they might offer promise for further research in this complex environment. Most scheduling and control systems are data intensive and require real-time feedback. Our research explores the use of simple, limited data, flow control mechanisms. The results indicate that these newer planning and control mechanisms, which offer a systems perspective, perform well when compared with a real time, data-intensive, flow control mechanism.     

Tool procurement planning for wafer fabrication facilities: a scenario-based approach

The rate of change in technology in the semiconductor industry has made the demand supply planning process extremely challenging for manufacturers. This problem is further exacerbated for tool procurement because the tools are made to order, very expensive and have a long lead time for delivery. In this paper, we present a scenario-based stochastic planning approach for tool procurement under uncertainty in demand and formulate the problem as a mixed integer program. Our results based on the data from a manufacturing line indicate that the heuristics for stochastic planning can significantly outperform deterministic planning.     

A dynamic WIP control strategy for bottlenecks in a wafer fabrication system

The performance of a wafer fabrication system is constrained by its bottlenecks, which are difficult to detect and improve due to the complexity within the system. To weaken the negative effects of bottlenecks, a work in process (WIP) strategy is proposed in this paper which focuses on offline target WIP level setting and online WIP control simultaneously. First, bottlenecks are detected and classified based on the constraint weights which are decided by the sensitivity of the system performance to the machine's fluctuant availability. Second, the target WIP level is allocated to the bottlenecks to avoid the process fluctuation caused by unpredictable events. Third, in real time scheduling, the upstream machine of the bottlenecks modifies its dispatching order to adjust the deviation of the WIP levels at the bottlenecks. Finally, a simulation platform is developed to validate the effectiveness of the proposed method.     

AMHS capacity determination model for wafer fabrication based on production performance optimization

Automatic material handling system (AMHS) is becoming more important in 300?mm wafer fabrication factories (fab). Effective and efficient design and control of AMHS has become more critical particularly in capacity planning. The major concept of the AMHS capacity determination model is to maintain the originally designed optimal production throughput or cycle time of products. In order to maintain fab’s throughput or cycle time of products, WIP (work in process) portfolio of the constraint or the fastest workstation should be kept. Based on this concept, a GI/G/m queuing model based on FCFS (First-come-first-serve) dispatching rule of AMHS is applied to determine the required number of vehicles. Basically, products should be transported to the specific workstation (constraint or fastest workstation) before the workstation finishes the existing process; therefore, sufficient WIP in front of this specific workstation should be kept. Under this condition, the probability that transportation time exceeds product processing time under a certain transportation capacity level can be calculated by the proposed model. Hence, we can get the required capacity of AMHS to achieve the probability target set in advance. Due to the capacity of AMHS can be set according to the acceptable probability of non-exceeding the processing time of the constraint or fastest workstation, the level of WIP in front of this workstation can be kept. It also can be ensured that AMHS will not affect the production performance as well as keep the reasonable investment level.     

MR head wafer fabrication technology: current and futureperspectives

Areal storage densities and yield requirements continuously drive process optimizations in volume manufacturing of magnetoresistive (MR) heads. Several topics related to the manufacturability of MR heads are discussed. A dependable supply of MR sputter targets with low magnetostriction λ_s is critical. By using an internally developed technique, λ_s can be predicted to within ±1.0×10^-7. MR film thickness uniformity can be improved by 60% by synchronizing the shutter activation with the substrate table. The profile of the photoresist for the read trackwidth definition is affected by initial exposure dose and post expose bake temperature. The use of mass-spectrometric and optical emission endpoint detection methods during ion beam etching of the MR layers allows a precise determination of the stopping point without overmilling into the layer underneath     

Simulation analysis of dispatching rules for an automated interbay material handling system in wafer fab

Here, the performance evaluation of a double-loop interbay automated material handling system (AMHS) in wafer fab was analysed by considering the effects of the dispatching rules. Discrete event simulation models based on SIMPLE++ were developed to implement the heuristic dispatching rules in such an AMHS system with a zone control scheme to avoid vehicle collision. The layout of an interbay system is a combination configuration in which the hallway contains double loops and the vehicles have double capacity. The results show that the dispatching rule has a significant impact on average transport time, waiting time, throughput and vehicle utilization. The combination of the shortest distance with nearest vehicle and the first encounter first served rule outperformed the other rules. Furthermore, the relationship between vehicle number and material flow rate by experimenting with a simulation model was investigated. The optimum combination of these two factors can be obtained by response surface methodology.     

Toward wafer scale fabrication of graphene based spin valve devices

We demonstrate injection, transport, and detection of spins in spin valve arrays patterned in both copper based chemical vapor deposition (Cu-CVD) synthesized wafer scale single layer and bilayer graphene. We observe spin relaxation times comparable to those reported for exfoliated graphene samples demonstrating that chemical vapor deposition specific structural differences such as nanoripples do not limit spin transport in the present samples. Our observations make Cu-CVD graphene a promising material of choice for large scale spintronic applications.     

Using in-line equipment condition and yield information for maintenance scheduling and dispatching in semiconductor wafer fabs

Yield is one of the most important measures of manufacturing performance in the semiconductor industry, and equipment condition plays a critical role in determining yield. Researchers and practitioners alike have traditionally treated the problems of equipment maintenance scheduling and production dispatching independently, ignoring how equipment condition may affect different product types or families in different ways. This paper addresses the problem of how to schedule maintenance and production for a multiple-product, multiple-stage production system. The problem is based on the situation found in semiconductor wafer fabrication where the equipment condition deteriorates over time, and this condition affects the yield of the production process. We extend a recently developed Markov decision process model of a single-stage system to account for the fact that semiconductor wafers have multiple layers and thus make repeated visits to each workstation. We then propose a methodology by which the single-stage results can be applied in a multi-stage system. Using a simulation model of a four-station wafer fab, we test the policies generated by the model against a variety of other maintenance and dispatching policy combinations. The results indicate that our method provides substantial improvements over traditional methods and performs better as the diversity of the product set increases. In the scenarios examined, the reward earned using the policies from the combined production and maintenance scheduling method was an average of more than 70° higher than the reward earned using other policy combinations such as a fixed-state maintenance policy and a first-come, first-serve dispatching policy.     

A performance analytical model of automated material handling system for semiconductor wafer fabrication system

To effectively analyse and evaluate the performances of closed-loop automated material handling system (AMHS) with shortcut and blocking in semiconductor wafer fabrication system, a modified Markov chain model (MMCM) has been proposed. The system characteristics, such as vehicle blockage and system’s shortcut configuration, are well considered in the MMCM. The state space explosion problem and computational challenge due to the increase of AMHS scale can be effectively eliminated. With production data from Interbay material handling system of a 300-mm semiconductor wafer fabrication line, the proposed MMCM is compared with simulation analysis model. The results demonstrate that the proposed MMCM is an effective modelling methodology for AMHS’s performance analysis at system design stage.