Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently, machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductor manufacturing. The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features. This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns. First, the number of defects during the actual process may be limited. Therefore, insufficient data are generated using convolutional auto-encoder (CAE), and the expanded data are verified using the evaluation technique of structural similarity index measure (SSIM). After extracting handcrafted features, a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction. Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns, the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.     

Development of a real-time multi-objective scheduler for a semiconductor fabrication system

Semiconductor wafer fabrication involves possibly one of the most complex manufacturing processes ever used. This causes a number of decision problems. A successful system control strategy would assign appropriate decision rules for decision variables. Therefore, the goal of this study is to develop a scheduler for the selection of decision rules for decision variables in order to obtain the desired performance measures given by a user at the end of a certain production interval. In this proposed methodology, a system control strategy based on a simulation technique and a competitive neural network is suggested. A simulation experiment was conducted to collect the data containing the relationship between the change of decision rule set and current system status and the performance measures in the dynamic nature of semiconductor manufacturing fabrication. Then, a competitive neural network was applied to obtain the scheduling knowledge from the collected data. The results of the study indicate that applying this methodology to obtaining a control strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.     

A novel hybrid resampling for semiconductor wafer defect bin classification

Generally, defective dies on semiconductor wafer maps tend to form spatial clusters in distinguishable patterns which contain crucial information on specific problems of equipment or process, thus it is highly important to identify and classify diverse defect patterns accurately. However, in practice, there exists a serious class imbalance problem, that is, the number of the defective dies on semiconductor wafer maps is usually much smaller than that of the non-defective dies. In various machine learning applications, a typical classification algorithm is, however, developed under the assumption that the number of instances for each class is nearly balanced. If the conventional classification algorithm is applied to a class imbalanced dataset, it may lead to incorrect classification results and degrade the reliability of the classification algorithm. In this research, we consider the semiconductor wafer defect bin data combined with wafer warpage information and propose a new hybrid resampling algorithm to improve performance of classifiers. From the experimental analysis, we show that the proposed algorithm provides better classification performance compared to other data preprocessing methods regardless of classification models.     

Wafer bin map recognition using a neural network approach

Although the fabrication of modern integrated circuits uses highly automatic and precisely controlled operations, equipment malfunctions or process drifts are still inevitable owing to the high complexity involved in the hundreds of processing steps. To detect the existence of these problems at the earliest stage, some important analytical tools must be applied. Among them is wafer bin map analysis. When the bin map exhibits specific patterns, it is usually a clue that equipment problems or process variations have occurred. The aim was to develop an intelligent system that could automatically recognize wafer bin map patterns and aid in the diagnosis of failure causes. A neural network architecture named Adaptive Resonance Theory Network 1 was adopted for the purpose. Actual data collected from a semiconductor manufacturing company in Taiwan were used for system verification. Experimental results show that with an adequate parameter, the neural network can successfully recognize and distinguish random and systematic wafer bin map patterns.     

Convolutional and generative adversarial neural networks in manufacturing

Manufacturing is undergoing transformation driven by the developments in process technology, information technology, and data science. A future manufacturing enterprise will be highly digital. This will create opportunities for machine learning algorithms to generate predictive models across the enterprise in the spirit of the digital twin concept. Convolutional and generative adversarial neural networks have received some attention of the manufacturing research community. Representative research and applications of the two machine learning concepts in manufacturing are presented. Advantages and limitations of each neural network are discussed. The paper might be helpful in identifying research gaps, inspire machine learning research in new manufacturing domains, contribute to the development of successful neural network architectures, and getting deeper insights into the manufacturing data.     

Data transformation in SPC for semiconductor machinery control: A case of monitoring particles

Yield is an important indicator of productivity in semiconductor manufacturing. In the complex manufacturing process, the particles on wafers inevitably cause defects, which may result in chip failure and thus reduce yield. Semiconductor manufacturers initially use wafer testing to control the machine for the number of particles. This machinery control procedure aims to detect any unusual condition of machines, reduce defects in actual wafer production and thus improve yield. In practice, the distribution of particles does not usually follow a Poisson distribution, which causes an overly high rate of false alarms in applying the c-chart. Consequently, the semiconductor machinery cannot be appropriately controlled by the number of particles on machines. This paper primarily combines data transformation with the control chart based on a Neyman type-A distribution to develop a machinery control procedure applicable to semiconductor machinery. The proposed approach monitors the number of particles on the testing wafer of machines. A semiconductor company in Taiwan in the Hsinchu Science Based Industrial Park demonstrated the feasibility of the proposed method through the implementation of several machines. The implementation results indicated that the occurrence of false alarms declined extensively from 20% to 4%.     

Economic in-line inspection sampling strategy with learning effects

This paper presents an innovative approach to a wafer inspection strategy that incorporates learning dynamics in semiconductor manufacturing factories. Using the data from fabrication lines (fabs) we demonstrate algorithms for computing the sampling strategy in terms of the percentage of wafers to sample for a process in different phases of a product life cycle. The average selling price and wafer starts per weeks are considered in the model. The paper provides an optimal solution methodology and concludes that the learning benefits of quality control activities may achieve the most cost-effective operations.     

Analysing semiconductor manufacturing big data for root cause detection of excursion for yield enhancement

With the shrinking feature size of integrated circuits driven by continuous technology migrations for wafer fabrication, the control of tightening critical dimensions is critical for yield enhancement, while physical failure analysis is increasingly difficult. In particular, the yield ramp up stage for implementing new technology node involves new production processes, unstable machine configurations, big data with multiple co-linearity and high dimensionality that can hardly rely on previous experience for detecting root causes. This research aims to propose a novel data-driven approach for Analysing semiconductor manufacturing big data for low yield (namely, excursions) diagnosis to detect process root causes for yield enhancement. The proposed approach has shown practical viability to efficiently detect possible root causes of excursion to reduce the trouble shooting time and improve the production yield effectively.     

基于AHP和规则的多目标晶圆制造派工方法的应用

针对半导体晶圆制造系统调度的时变多目标特性,提出基于AHP和规则的多目标派工方法,在不同时期,赋予各调度目标不同的权重,通过仿真实验得到判断矩阵,然后用层次分析法来选择各设备的派工规则,并进行了敏感性分析,为半导体晶圆制造系统的科学管理提供了有效的实现途径.     

A hierarchical model for characterising spatial wafer variations

Silicon wafers are commonly used materials in the semiconductor manufacturing industry. Their geometric quality directly affects the production cost and yield. Therefore, improvement in the quality of wafers is critical for meeting the current competitive market needs. Conventional summary metrics such as total thickness variation, bow and warp can neither fully reflect the local variability within each wafer nor provide useful insight for root cause diagnosis and quality improvement. The advancement of sensing technology enables two-dimensional (2D) data mapping to characterise the geometric shapes of wafers, which provides more information than summary metrics. The objective of this research is to develop a statistical model to characterise the thickness variation of wafers based on 2D data maps. Specifically, the thickness variation of wafers is decomposed into macro-scale and micro-scale variations, which are modelled as a cubic curve and a first-order intrinsic Gaussian Markov random field, respectively. The models can successfully capture both the macro-scale mean trend and the micro-scale local variation, with important engineering implications for process monitoring, fault diagnosis and run-to-run control. A practical case study from a wafer manufacturing process is performed to show the effectiveness of the proposed methodology.     

Defect pattern recognition on wafers using convolutional neural networks

In semiconductor manufacturing, wafer testing is performed to ensure the performance of each product after wafer fabrication. The wafer map is used to visualize the color-coded wafer test results based on the locations. The defects on the wafer map may be randomly distributed or form clustered patterns. The various clustered defect patterns are usually caused by assignable faults. The identification of the patterns is thus important to provide valuable hints for the root causes diagnosis. Solving the problems helps improve the manufacturing processes and reduce costs. In this study, we present a novel convolutional neural network (CNN)–based method to automatically recognize the defect pattern on wafer maps. Our method uses polar mapping before the training of CNN to transform the circular wafer map into a matrix, which can be processed within CNN architecture. This procedure also reduces the input size and solves variations in wafer sizes and die sizes. To eliminate the effects of rotation, we apply data augmentation in the training of CNN. Experiments using the real-world dataset prove the effectiveness and superiority of our method.     

Modular Neural Network Architecture for Precise Condition Monitoring

Unplanned production shutdown due to equipment failure is the source of the highest cost in the manufacturing and process industries. Traditional fault detection methods are able to monitor the process and detect deterioration of the equipment after their degradation and malfunction occurs. This paper presents an intelligent technique based on a neural network (NN) that monitors the health of the equipment and forecasts faults by detecting any onset of failures. In this approach, an adaptive modular NN architecture that is capable of monitoring the health of industrial machines is introduced. This technique is applied to a subsystem of a machining center. The high accuracy of the technique is verified by extensive tests, resulting in over 99% precision.     

A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.     

Fuzzy neural network based yield prediction model for semiconductor manufacturing system

Accurate die yield prediction is very useful for improving yield, decreasing cost and maintaining good relationships with customers in the semiconductor manufacturing industry. To improve prediction accuracy of die yield, a novel fuzzy neural networks based yield prediction model is proposed in which the impact factors of yield and critical electrical test parameters are considered simultaneously and are taken as independent variables. The mapping between these independent variables and yield is constructed in the fuzzy neural network (FNN). The lineal regression between FNN-based yield predicting output and actual yield demonstrates the effectiveness of the proposed approach by historical experimental data of semiconductor fabrication line in Shanghai. The comparison experiment verifies the proposed yield prediction method improves on three traditional yield prediction methods with respect to prediction accuracy.     

Prediction and optimization of a ceramic casting process using a hierarchical hybrid system of neural networks and fuzzy logic

This paper is a case study that describes a hybrid system integrating fuzzy logic, neural networks and algorithmic optimization for use in the ceramics industry. A prediction module estimates two quality metrics of slip-cast pieces through the simultaneous execution of two neural networks. A process improvement algorithm optimizes controllable process settings using the neural network prediction module in the objective function. An expert system module contains a hierarchy of two fuzzy logic rule bases. The rule bases prescribe processing times customized to individual production lines given ambient conditions, mold characteristics and the neural network predictions. This paper demonstrates the applicability of newer computational techniques to a very traditional manufacturing process and the system has been implemented at a major US plant.     

Selection of dispatching rules on multiple dispatching decision points in real-time scheduling of a semiconductor wafer fabrication system

Semiconductor wafer fabrication involves one of the most complex manufacturing processes ever used. To control such complex systems, it is a challenge to determine appropriate dispatching strategies under various system conditions. Dispatching strategies are classified into two categories: a vehicle-initiated dispatching policy and a machine-initiated dispatching policy. Both policies are important to improve the system performance, especially for the real time control of the system. However, there has been little research focusing on combining them under various situations for the semiconductor manufacturing system. In addition, it is shown that no single dispatching strategy consistently dominates others in all situations. Therefore, the goal of this study is to develop a scheduler for selection of dispatching rules for dispatching decision variables in order to obtain the desired performance measures given by a user for each production interval. For the proposed methodology, simulation and competitive neural network approaches are used. The results of the study indicate that applying our methodology to obtaining a dispatching strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.     

Using in-line equipment condition and yield information for maintenance scheduling and dispatching in semiconductor wafer fabs

Yield is one of the most important measures of manufacturing performance in the semiconductor industry, and equipment condition plays a critical role in determining yield. Researchers and practitioners alike have traditionally treated the problems of equipment maintenance scheduling and production dispatching independently, ignoring how equipment condition may affect different product types or families in different ways. This paper addresses the problem of how to schedule maintenance and production for a multiple-product, multiple-stage production system. The problem is based on the situation found in semiconductor wafer fabrication where the equipment condition deteriorates over time, and this condition affects the yield of the production process. We extend a recently developed Markov decision process model of a single-stage system to account for the fact that semiconductor wafers have multiple layers and thus make repeated visits to each workstation. We then propose a methodology by which the single-stage results can be applied in a multi-stage system. Using a simulation model of a four-station wafer fab, we test the policies generated by the model against a variety of other maintenance and dispatching policy combinations. The results indicate that our method provides substantial improvements over traditional methods and performs better as the diversity of the product set increases. In the scenarios examined, the reward earned using the policies from the combined production and maintenance scheduling method was an average of more than 70° higher than the reward earned using other policy combinations such as a fixed-state maintenance policy and a first-come, first-serve dispatching policy.     

Forecasting flow time in semiconductor manufacturing using knowledge discovery in databases

Semiconductor manufacturing is characterised by a complex production process, advanced equipment, and volatile demand. Flow time (FT), noted cycle time in semiconductor manufacturing, is a key measure in the operations. This study develops FT forecasting models using knowledge discovery in databases. It follows cross industry standards for data mining, with the focus on business understanding, data pre-processing and classification techniques. The data include wafer lot transactions extracted from the manufacturing execution system of an 8-inch flash memory factory. The FT is forecasted for a single lot at a given production step. The models are constructed using 70% of the data and the rest 30% for their evaluation. The results illustrate that a decision tree model achieves 76.7% accuracy and a neural network model 88.2%. The novelty of this work is in a thorough understanding of operations, a single data source, and common classification techniques used to obtain high accuracy results. The models can generate FT forecasting for a single production step, a line segment or a complete line. They can be used to improve short term planning, overall operations and supply chain efficiency, via shift scheduling, labour and materials requirements planning, inventory management and delivery schedules.     

基于数据驱动仿真的两设备系统元模型

半导体封装测试系统等复杂制造系统的性能分析是项非常困难的任务。利用仿真模型构建两设备系统元模型,并以元模型为基石构建面向大规模复杂系统的近似解析方法是分析复杂制造系统的有效手段。为了快速准确地构建两设备系统元模型,提出了一种基于数据驱动仿真技术及人工神经网络的元模型构建方法。该方法以考虑缓存输送时间的两设备制造系统为研究对象,采用AREAN的二次开发技术实现仿真模型的自动配置、运行、统计,以生成人工神经网络所需案例,并通过比较分析BP、RBF和Chebyshev这3类典型的函数逼近神经网络确定最优的人工神经网络模型。实验结果表明径向基函数密度为120的RBF神经网络模型表现最优,其结果误差最小,能够成为大规模复杂制造系统近似解析方法的基石。     

Recognition of machining features - a hybrid approach

This paper describes a hybrid system which endeavours to recognize machining features automatically from a boundary representation (b-rep)-based solid modeller. The graph-based approach and the volume approach are adopted in consecutive stages in a prototype feature recognition system to combine the positive aspects of both strategies. The graph-based approach is based on feature edge sequence (FES) graph, a new graph structure introduced in this system. The FES graph approach is used to extract primitive features from the three-dimensional solid model; and the volume decomposition approach is incorporated to generate multiple interpretations of the feature sets. In addition, a neural network (NN)-based technique is used to tackle the problem of nonorthogonal and arbitrary features. Using the hybrid system, a workpiece designed in b-rep solid modeller will be interpreted and represented by a set of primitive features attached with significant manufacturing parameters, including multiple interpretations, tool directions and machining sequences, etc. The overall hybrid system is able to transform a pure geometric model into a machining feature-based model which is directly applicable for downstream manufacturing applications.