Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers

The integrated circuits (ICs) on wafers are highly vulnerable to defects generated during the semiconductor manufacturing process. The spatial patterns of locally clustered defects are likely to contain information related to the defect generating mechanism. For the purpose of yield management, we propose a multi-step adaptive resonance theory (ART1) algorithm in order to accurately recognise the defect patterns scattered over a wafer. The proposed algorithm consists of a new similarity measure, based on the p-norm ratio and run-length encoding technique and pre-processing procedure: the variable resolution array and zooming strategy. The performance of the algorithm is evaluated based on the statistical models for four types of simulated defect patterns, each of which typically occurs during fabrication of ICs: random patterns by a spatial homogeneous Poisson process, ellipsoid patterns by a multivariate normal, curvilinear patterns by a principal curve, and ring patterns by a spherical shell. Computational testing results show that the proposed algorithm provides high accuracy and robustness in detecting IC defects, regardless of the types of defect patterns residing on the wafer.     

Data transformation in SPC for semiconductor machinery control: A case of monitoring particles

Yield is an important indicator of productivity in semiconductor manufacturing. In the complex manufacturing process, the particles on wafers inevitably cause defects, which may result in chip failure and thus reduce yield. Semiconductor manufacturers initially use wafer testing to control the machine for the number of particles. This machinery control procedure aims to detect any unusual condition of machines, reduce defects in actual wafer production and thus improve yield. In practice, the distribution of particles does not usually follow a Poisson distribution, which causes an overly high rate of false alarms in applying the c-chart. Consequently, the semiconductor machinery cannot be appropriately controlled by the number of particles on machines. This paper primarily combines data transformation with the control chart based on a Neyman type-A distribution to develop a machinery control procedure applicable to semiconductor machinery. The proposed approach monitors the number of particles on the testing wafer of machines. A semiconductor company in Taiwan in the Hsinchu Science Based Industrial Park demonstrated the feasibility of the proposed method through the implementation of several machines. The implementation results indicated that the occurrence of false alarms declined extensively from 20% to 4%.     

A model-based clustering approach to the recognition of the spatial defect patterns produced during semiconductor fabrication

Defects on semiconductor wafers tend to cluster and the spatial defect patterns of these defect clusters contain valuable information about potential problems in the manufacturing processes. This study proposes a model-based clustering algorithm for automatic spatial defect recognition on semiconductor wafers. A mixture model is proposed to model the distributions of defects on wafer surfaces. The proposed algorithm can find the number of defect clusters and identify the pattern of each cluster automatically. It is capable of detecting defect clusters with linear patterns, curvilinear patterns and ellipsoidal patterns. Promising results have been obtained from simulation studies.     

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently, machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductor manufacturing. The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features. This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns. First, the number of defects during the actual process may be limited. Therefore, insufficient data are generated using convolutional auto-encoder (CAE), and the expanded data are verified using the evaluation technique of structural similarity index measure (SSIM). After extracting handcrafted features, a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction. Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns, the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.     

A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.     

Part dimension deviation control in batch manufacturing process for monitoring error sources

In a batch manufacturing process a cross-correlation exists among dimension deviations of different parts. The modelling and control of these deviations are essential to improve product dimension quality. Traditional dimension deviation statistical control methods have been focused on retrospectively analysing part dimension feature, while based on the spatial relationship between part dimensional features and error sources showed in part dimension error propagation model, this paper presents a method to control part dimension deviation in batch manufacturing that focuses on error sources. At each operation, total part deviation is separated into three components corresponding to three error sources. Therefore, a multivariate exponentially weighted moving average (MEWMA) chart for error sources is proposed to control part dimension deviations with identified error sources attribute to part dimension deviation. Efficiency and reliability of this model were verified by simulation analysis in common error source abnormal patterns, and the model is proved to be effective for detecting small deviations in a batch manufacturing process.     

An empirical study of demand forecasting of non-volatile memory for smart production of semiconductor manufacturing

As high-speed computing is crucial to empower intelligent manufacturing for Industry 4.0, non-volatile memory (NVM) is critical semiconductor component of the cloud and data centre for the infrastructures. The NVM manufacturing is capital intensive, in which capacity utilisation significantly affects the capital effectiveness and profitability of semiconductor companies. Since capacity migration and expansion involve long lead times, demand forecasting plays a critical role for smart production of NVM manufacturers for revenue management. However, the shortening product life cycles of integrated circuits (IC), the fluctuations of semiconductor supply chains, and uncertainty involved in demand forecasting make the present problem increasingly difficult in the consumer electronics era. Focusing on the realistic needs of NVM demand forecasting, this study aims to develop a decision framework that integrates an improved technology diffusion model and a proposed adjustment mechanism to incorporate domain insights. An empirical study was conducted in a leading semiconductor company for validation. A comparison of alternative approaches is also provided. The results have shown the practical viability of the proposed approach.     

A spatial variable selection method for monitoring product surface

Two-dimensional (2-D) data maps are generated in certain advanced manufacturing processes. Such maps contain rich information about process variation and product quality status. As a proven effective quality control technique, statistical process control (SPC) has been widely used in different processes for shift detection and assignable cause identification. However, charting algorithms for 2-D data maps are still vacant. This paper proposes a variable selection-based SPC method for monitoring 2-D wafer surface. The fused LASSO algorithm is firstly employed to identify potentially shifted sites on the surface; a charting statistic is then developed to detect statistically significant shifts. As the variable selection algorithm can nicely preserve shift patterns in spatial clusters, the newly proposed chart is proved to be both effective in detecting shifts and capable of providing diagnostic information for process improvement. Extensive Monte Carlo simulations and a real example have been used to demonstrate the effectiveness and usage of the proposed method.     

Automatic identification of spatial defect patterns for semiconductor manufacturing

This research proposes an on-line diagnosis system based on denoising and clustering techniques to identify spatial defect patterns for semiconductor manufacturing. Today, even with highly automated and precisely monitored facilities used in a near dust-free clean room and operated with well-trained process engineers, the occurrence of spatial signatures on the wafer still cannot be avoided. Typical defect patterns shown on the wafer, including edge ring, linear scratch, zone type and mixed type, usually contain important information for quality engineers to remove their root causes of failures. In this paper, a spatial filter is simultaneously used to judge whether the input data contains any systematic cluster and to extract it from the noisy input. Then, an integrated clustering scheme combining fuzzy C means (FCM) with hierarchical linkage is adopted to separate various types of defect patterns. Furthermore, a decision tree based on two cluster features (convexity and eigenvalue ratio) is applied to a separated pattern to provide decision support for quality engineers. Experimental results show that both real dataset and synthetic dataset have been successfully extracted and classified. More importantly, the proposed method has potential to be further applied to other industries, such as liquid crystal display (LCD) and plasma display panel (PDP).     

A genetic scheduling methodology for virtual cellular manufacturing systems: an industrial application

Effective solutions to the cell formation and the production scheduling problems are vital in the design of virtual cellular manufacturing systems (VCMSs). This paper presents a new mathematical model and a scheduling algorithm based on the techniques of genetic algorithms for solving such problems. The objectives are: (1) to minimize the total materials and components travelling distance incurred in manufacturing the products, and (2) to minimize the sum of the tardiness of all products. The proposed algorithm differs from the canonical genetic algorithms in that the populations of candidate solutions consist of individuals of different age groups, and that each individual's birth and survival rates are governed by predefined aging patterns. The condition governing the birth and survival rates is developed to ensure a stable search process. In addition, Markov Chain analysis is used to investigate the convergence properties of the genetic search process theoretically. The results obtained indicate that if the individual representing the best candidate solution obtained is maintained throughout the search process, the genetic search process converges to the global optimal solution exponentially.

The proposed methodology is applied to design the manufacturing system of a company in China producing component parts for internal combustion engines. The performance of the proposed age-based genetic algorithm is compared with that of the conventional genetic algorithm based on this industrial case. The results show that the methodology proposed in this paper provides a simple, effective and efficient method for solving the manufacturing cell formation and production scheduling problems for VCMSs.     

Wafer yield prediction using derived spatial variables

Unreliable chips tend to form spatial clusters on semiconductor wafers. The spatial patterns of these defects are largely reflected in functional testing results. However, the spatial cluster information of unreliable chips has not been fully used to predict the performance in field use in the literature. This paper proposes a novel wafer yield prediction model that incorporates the spatial clustering information in functional testing. Fused LASSO is first adopted to derive variables based on the spatial distribution of defect clusters. Then, a logistic regression model is used to predict the final yield (ratio of chips that remain functional until expected lifetime) with derived spatial covariates and functional testing values. The proposed model is evaluated both on real production wafers and in an extensive simulation study. The results show that by explicitly considering the characteristics of defect clusters, our proposed model provides improved performance compared to existing methods. Moreover, the cross‐validation experiments prove that our approach is capable of using historical data to predict yield on newly produced wafers.     

General run-to-run (R2R) control framework using self-tuning control for multiple-input multiple-output (MIMO) processes

During recent years, run-to-run (R2R) control techniques have been developed and used to control various semiconductor manufacturing processes. The R2R control methodology combines response surface modelling, engineering process control, and statistical process control. The main objective of such control is to manipulate the recipe to maintain the process output of each run as close to the nominal target as possible. The primary focus of this research is on the multiple-input multiple-output self-tuning control of R2R processes. A general control scheme is presented that can compensate for a variety of noise disturbances frequently encountered in semiconductor manufacturing. The controller can also compensate for various system dynamics, including autocorrelated responses, deterministic drifts, and varying process gains and offsets. Self-tuning controllers are developed to provide on-line parameter estimation and control. A recursive least squares algorithm is normally used to provide on-line parameter estimation to the controller. This type of control strategy used in the proposed self-tuning controller applies the principle of minimizing total cost (in the form of an expected off-target and controllable factors adjustment) to obtain a recipe for the next run. It is shown through the simulation study that even if the control model is non-linear, the self-tuning controller offers satisfactory control performance for R2R applications as compared with those of the control actions provided by the optimizing adaptive quality controller module. At last, a relevant application to chemical mechanical planarization in semiconductor manufacturing, a critical fabrication step involving two quality characteristics (removal rate and within-wafer non-uniformity), is used to illustrate the proposed controller. In this case study, a multivariate statistical process control technique via the Hotelling T?² statistic is also used as a dead-band for further investigation.     

A multi-criteria decision-making approach for capacity allocation problem in semiconductor fabrication

In today's highly competitive environment, good customer relationship management is essential for a company to survive and to acquire reasonable profit. A semiconductor enterprise has multi-site fabs, and follows basically a make-to-order production type. The allocation of capacity for manufacturing different types of products is important for the competitiveness and future development of the enterprise. To cope with this requirement, a multi-criteria decision-making approach is proposed in this article for more efficient evaluation and selection of capacity allocation plans in semiconductor fabs. Under this approach, fuzzy analytic network process (FANP) is incorporated with fuzzy Delphi method (FDM), constraint programming (CP) and benefits, opportunities, costs and risks (BOCR). FDM is used to achieve a consensus among the opinions of experts. CP is used to screen out a set of capacity allocation plans that should be further evaluated. FANP with BOCR is used to evaluate the various factors and the interrelationship among the factors under the BOCR merits and to determine the expected performance of the capacity allocation plans. The proposed approach can provide a ranking and also priorities of different capacity allocation plans, and the fab can select the most appropriate capacity allocation for production in the case that insufficient capacity existed.     

Multistage PRIM: patient rule induction method for optimisation of a multistage manufacturing process

Industries such as automotive, LCD, PDP, semiconductor and steel produce products through multistage manufacturing processes. In a multistage manufacturing process, performances of stages are not independent. Therefore, the relationship between stages should be considered when optimising the multistage manufacturing process. This study proposes a new procedure of optimising a multistage manufacturing process, called multistage PRIM (patient rule induction method). Multistage PRIM extends the scope of process optimisation from a single stage to the multistage process, and it can use the information encapsulated in the relationship between stages when maximising each stage's performance. A case study in a multistage steel manufacturing process is conducted to illustrate the proposed procedure.     

Stacked denoising autoencoder‐based feature learning for out‐of‐control source recognition in multivariate manufacturing process

In multivariate statistical process control (MSPC), regular multivariate control charts (eg, T²) are shown to be effective in detecting out‐of‐control signals based upon an overall statistic. But these charts do not relieve the need for multivariate process pattern recognition (MPPR). MPPR would be very useful for quality operators to locate the assignable causes that give rise to out‐of‐control situation in multivariate manufacturing process. Deep learning has been widely applied and obtained many successes in image and visual analysis. This paper presents an effective and reliable deep learning method known as stacked denoising autoencoder (SDAE) for MPPR in manufacturing processes. This study will concentrate on developing a SDAE model to learn effective discriminative features from the process signals through deep network architectures. Feature visualization is performed to explicitly present feature representations of the proposed SDAE model. The experimental results illustrate that the proposed SDAE model is capable of implementing detection and recognition of various process patterns in complicated multivariate processes. Analysis from this study provides the guideline in developing deep learning‐based MSPC systems.     

提升台湾IC制造业竞争力之策略选择

首先介绍台湾IC产业之发展状况,然后进一步分析IC制造之竞争力,接着根据制造策略相关文献及业界专家意见访查,找出提升台湾IC制造竞争力之策略：设备利用率、先进制造技术、供货商关系、品质管制、人力资源,这些策略造就了台湾IC制造之竞争优势,也提供半导体制造管理之新典范。     

Analysing semiconductor manufacturing big data for root cause detection of excursion for yield enhancement

With the shrinking feature size of integrated circuits driven by continuous technology migrations for wafer fabrication, the control of tightening critical dimensions is critical for yield enhancement, while physical failure analysis is increasingly difficult. In particular, the yield ramp up stage for implementing new technology node involves new production processes, unstable machine configurations, big data with multiple co-linearity and high dimensionality that can hardly rely on previous experience for detecting root causes. This research aims to propose a novel data-driven approach for Analysing semiconductor manufacturing big data for low yield (namely, excursions) diagnosis to detect process root causes for yield enhancement. The proposed approach has shown practical viability to efficiently detect possible root causes of excursion to reduce the trouble shooting time and improve the production yield effectively.     

Defect pattern recognition on wafers using convolutional neural networks

In semiconductor manufacturing, wafer testing is performed to ensure the performance of each product after wafer fabrication. The wafer map is used to visualize the color-coded wafer test results based on the locations. The defects on the wafer map may be randomly distributed or form clustered patterns. The various clustered defect patterns are usually caused by assignable faults. The identification of the patterns is thus important to provide valuable hints for the root causes diagnosis. Solving the problems helps improve the manufacturing processes and reduce costs. In this study, we present a novel convolutional neural network (CNN)–based method to automatically recognize the defect pattern on wafer maps. Our method uses polar mapping before the training of CNN to transform the circular wafer map into a matrix, which can be processed within CNN architecture. This procedure also reduces the input size and solves variations in wafer sizes and die sizes. To eliminate the effects of rotation, we apply data augmentation in the training of CNN. Experiments using the real-world dataset prove the effectiveness and superiority of our method.     

Event-driven multi-agent ubiquitous manufacturing execution platform for shop floor work-in-progress management

It has been reported that radio frequency identification (RFID) technology is applied to manufacturing shop floors for capturing and collecting real-time field data. Real-time information visibility and traceability allows decision makers to make better-informed shop floor decisions. It has been a great challenge to process a huge amount of RFID data into useful information for managerial uses. This paper presents an event-driven shop floor work-in-progress (WIP) management platform for creating a ubiquitous manufacturing (UM) environment. The platform aims to monitor and control dynamic production and material handling through RFID-enabled traceability and visibility of shop floor manufacturing processes. The platform provides facilities to process shop floor real-time RFID events and to aggregate actionable and meaningful operational information to support decision-making activities. An information processing mechanism based on a critical event model is proposed to organise real-time field data in various abstract levels for enterprise decisions. A case study at an air conditioner manufacturing company is used to demonstrate how the proposed platform can benefit its shop floor WIP management by showing how production and logistic operators and their supervisors accomplish their tasks.     

A hybrid scheduling approach for automated flowshops with material handling and time constraints

Flowshop scheduling problems have been extensively studied by several authors using different approaches. A typical flowshop process consists of successive manufacturing stages arranged in a single production line where different jobs have to be processed following a predefined production recipe. In this work, the scheduling of a complex flowshop process involving automated wet-etch station from semiconductor manufacturing systems requires a proper synchronisation of processing and transport operations, due to stringent storage policies and fixed transfer times between stages. Robust hybrid solution strategies based on mixed integer linear programming formulations and heuristic-based approaches, such as aggregation and decomposition methods, are proposed and illustrated on industrial-scale problems. The results show significant improvements in solution quality coupled with a reduced computational effort compared to other existing methodologies.