High-speed sensing scheme for CMOS DRAMs

A significant improvement in sensing speed over the half-V_DD bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V_DD. The 2/3-V_DD sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V_DD sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V_DD sensing with a limited bit-line swing has several distinct advantages over the half-V_DD sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs     

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devices

An experimental 11-ns 8 K×18 static RAM fabricated in a 1.2-μm CMOS technology with 0.5-μm channel lengths is described. Novel interface circuits allow full TTL-level compatibility with a scaled 3.6-V V_dd. Synchronous clocking and automatic restore operations were implemented to realize high-speed access and a fast cycle data rate of 8 ns. Double-word-line architecture and a pulsed word-line technique reduce power dissipation. Other features include on-chip test circuitry that increases tester timing accuracy and word-line redundancy. The design uses a single-poly, double-metal technology with a CMOS six-transistor cell of 235 μm² to yield a chip size of 60 mm²     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation     

Low-power on-chip supply voltage conversion scheme forultrahigh-density DRAMs

In order to achieve 3.3-V 1-Gb DRAM and beyond, a new on-chip supply voltage conversion scheme that converts 3.3-V external supply voltage, V_ext, to lowered 1.5-V internal supply voltage, V_ent, without any power loss within the voltage converter is proposed. This scheme connects two identical DRAM circuits in series between V_ixt and V_ss. By operation of two DRAM circuits with the same clock timing, the voltage between two DRAMs, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAMs. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty     

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V_cc), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V_cc DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V_cc of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3-μm electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs     

A 1.544-Mb/s CMOS line driver for a 22.8-Ω load

A CMOS line driver for high-speed data communication according to the T1 and CEPT recommendations is presented. The differential output swing is 7.2 V_pp on a load of 22.8 Ω from a single 5-V supply. A novel quiescent current control scheme is used. The driver occupies an area of 6.5 mm² using a 2-μm p-well CMOS technology     

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable referencebit-line voltage scheme using a fatigue-free reference capacitor

A 0.5-μm, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance C_ferr is larger than reference-cell capacitance C_MOS. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme     

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM     

Decoded-source sense amplifier for high-density DRAMs

The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V_cc of 4 V at 85°C     

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using aNAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm², and the effective cell size including the overhead of string select transistors is 2.0 μm²     

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted2.1-V word line

This paper describes the key technologies used in a 1-Gb synchronous DRAM. This DRAM was developed according to a new cell-operating concept in which a ground-level (V_ss) precharged bit line with a negative word-line reset scheme enables a nonboosted 2.1-V word-line architecture. Total power consumption is less than that of the conventional half-V_cc precharged bit-line scheme. We also propose a vernier-type, high-accuracy delay-locked-loop circuit realizing ±20-ps quantization errors for clock recovery and skew elimination     

A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

A 25-ns 4-Mbit CMOS SRAM with 512 K word*8-bit organization has been developed. The RAM was fabricated using a 0.5- mu m double-poly and double-aluminum CMOS technology and was assembled in a 32-pin 400-mil DIP. A small cell size of 3.6*5.875 mu m/sup 2/ and a chip size of 7.46*17.41 mm/sup 2/ were obtained. A fast address access time of 25 ns with a single 3.3-V supply voltage has been achieved using the newly developed dynamic bit-line load (DBL) circuit scheme incorporated with an address transition detector (ATD), divided word-line structure (DWL), three-stage sense amplifier, and low-noise output circuit approach. A low operating current of 46 mA at 40 MHz and low standby currents of 70 mu A (TTL) and 5 mu A (CMOS) were also attained.<>     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

Collector-assisted operation of micromachined field-emitter triodes

The field at the tip of a field emitter triode can be expressed by E=βV_g+_γV _c, where V_g and V_c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, _γV_c<<βV _g. The-device is operated in the gate-induced field emission mode and the corresponding I-V_c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-V_c and transconductance g_m-V_g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly     

A pseudomorphic AlGaAs/n+-InGaAs metal-insulator-dopedchannel FET for broad-band, large-signal applications

Molecular beam epitaxy (MBE)-grown L_g=1.7-μm pseudomorphic Al_0.38Ga_0.62As/n⁺-In_0.15Ga _0.85As metal-insulator-doped channel FETs (MIDFETs) are presented that display extremely broad plateaus in both f_T and f_max versus V_GS, with f_T sustaining 90% of its peak over a gate swing of 2.6 V. Drain current is highly linear with V_GS over this swing, reaching 514 mA/mm. No frequency dispersion in g _m up to 3 GHz was found, indicating the absence of electrically active traps in the undoped AlGaAs pseudoinsulator layer. These properties combine to make the pseudomorphic MIDFET highly suited to linear, large-signal, broadband applications     

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm/sup 2/ was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-/spl mu/m CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.     

Design of a bipolar 10-MHz programmable continuous-time 0.05°equiripple linear phase filter

A bipolar seventh-order 0.05° equiripple linear phase (constant group delay) transconductance-capacitor (g_m-C) low-pass filter with a cutoff frequency (f_c) tunable between 2 and 10 MHz is presented. Programmable equalization up to 9 dB at f_c is also provided. Total harmonic distortion at 2 V_p-p is less than 1%, with a dynamic range equal to 49 dB. Nominal power consumption from a single 5-V supply is 135 mW. The circuit also has a low-power mode (<0.5-mW dissipation)     

Half-VCC sheath-plate capacitor DRAM cell withself-aligned buried plate wiring

A trench-capacitor DRAM cell called a half-V_CC sheath-plate capacitor (HSPC) cell has been developed using 0.6-μm-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 μm² and excellent immunity (critical charge Q_c<35 fC) against alpha-particle injection. These advantages are achieved using a half-V_CC sheath-plate structure, a 5.5-nm SiO₂-equivalent Si ₃N₄-SiO₂ composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array     

Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress