Examination of degradation mechanism due to negative bias temperature stress from a perspective of hole energy for accurate lifetime prediction

An evaluation method using the modified hole injection method is proposed to evaluate Negative Bias Temperature Instability (NBTI) in this paper. The physical backgrounds of the evaluation method are strictly discussed. The proposed method accelerates the degradation such as the threshold voltage (V_th) shift by the amount of the hole injection without the high gate voltage stress. Our experimental and theoretical frameworks clarify that two degradation mechanisms, one follows the reaction–diffusion (R–D) model and another follows the hole trap/de-trap (HTD) model, coexist in NBTI. In the inversion layer, holes distributed in the quantized upper energy levels especially induce the degradation that follows the R–D model, and holes distributed in the ground energy level induce the degradation that follows the HTD model. Finally, the accurate NBTI lifetime prediction is demonstrated using the proposed acceleration method.     

Method to extract parameters of power law for nano-scale SiON pMOSFETs under negative bias temperature instability

This paper proposes a fast and accurate method to extract parameters of the power law for nano-scale SiON pMOSFETs under negative bias temperature instability (NBTI), which is useful for an accurate estimation of NBTI lifetime. Experimental results show that accurate extraction of the time exponent n of the power law was obstructed by either fast trapping of minority carriers or damage recovery during measurement of threshold voltage V_th. These obstructing effects were eliminated using ΔV_ths obtained from fast and slow measurement-stress-measurement (MSM) procedures. The experimental SiON pMOSFETs had n ≈ 1/4, an activation energy E_a = 0.04 eV for the fast recoverable degradation, and E_a = 0.2 eV for the slow permanent degradation. Based on these experimental observations, a method to estimate NBTI lifetime is proposed.     

Modelling negative bias temperature instabilities in advanced p-MOSFETs

The decrease of the threshold voltage V_th of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si₃Si^√ (P_b0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that V_th shifts are mainly due to the tunnelling of holes at low gate bias |V_G|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |V_G|. Consequently, device lifetime at operating voltage, based on V_th shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on V_th shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si---N---Si strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, V_th shifts in p-MOSFET with Hf_ySiO_x gate layers and SiO₂/Hf_ySiO_x gate stacks are simulated, taking into account the generation of P_b0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO₂/Hf_ySiO_x gate stacks as compared to single Hf_ySiO_x layers. This finding is attributed to the beneficial presence of the SiO₂ interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.     

Independent double-gate FinFETs with asymmetric gate stacks

Flexibly controllable threshold voltage (V_th) asymmetric gate oxide thickness (T_ox) independent double-gate (DG) FinFETs (4T-FinFETs) have been demonstrated. Thin drive-gate oxide (HfO₂ or SiON or SiO₂) and slightly thick V_th-control-gate oxide (thick SiO₂+drive-gate oxide) have been successfully incorporated into the 4T-FinFETs by utilizing the ion-bombardment-enhanced etching of SiO₂. It was experimentally confirmed that, all the asymmetric T_ox 4T-FinFETs give the significantly improved subthreshold slope and thus gain higher on-current as compared to the symmetric one. Simulation results showed that the asymmetric T_ox 4T-FinFETs are advantageous even in 20-nm-gate-length region.     

Performance enhancement of Poly-Si/TiN/SiON based pMOSFETs by addition of an aluminum oxide (AlO) capping layer

We investigate the influence of aluminum oxide (AlO) capping on SiON on the threshold voltage and I_on of Poly-Si/TiN gated pMOSFETs. The AlO capping resulted in threshold voltage (V_T) reduction and improvement in drive current (I_on) for Poly-Si/TiN/ gated pFETS. The AlO capping on SiON also improved the interface quality making the gate stack more thermally stable. The leakage and reliability characteristics for the Poly-Si/AlO/SiON stacks are evaluated and compared with the uncapped Poly-Si/TiN/SiON reference. The AlO capping resulted in two orders of magnitude decrease in leakage at the same capacitance equivalent thickness (CET) compared to the un-capped Poly-Si/TiN/SiON reference. The AlO capping also resulted in improvement lifetime compared to the un-capped Poly-Si/TiN/SiON reference.     

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO₂ gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, ΔV_TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO₂ interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO₂ interface (P_b centers) and its vicinity (E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I_D − V_G (ΔV_TH) techniques, however, suggests that ΔV_TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO₂/SiO₂ gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO₂ and high-k gate stacks suggesting a common mechanism of the interface degradation.     

Impact of NBTI and HCI on PMOSFET threshold voltage drift

Negative bias temperature instability (NBTI) induced PMOSFET parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies. In this paper, V_t-mismatch shift due to NBTI in a cascode current mirror is examined. The impact of NBTI and hot-carrier injection (HCI) on threshold voltage degradation and subsequent damage recovery during annealing is also studied. Finally the influence of channel length, gate voltage, drain voltage and damage recovery on conventional NBTI and HCI DC lifetime extrapolation is characterized with the impact on analog applications highlighted.     

NBTI and hot carrier effect of Schottky-barrier p-MOSFETs

The experimental investigation of NBTI and hot carrier induced device degradation in Pt-silicided Schottky-barrier p-MOSFETs has been performed. The investigations on the threshold voltage shifts, the degradation of inverse subthreshold slope, and the decrease of I_ON/I_OFF ratio have been carried out using the modulation of Schottky-barrier height and width. After NBTI and hot carrier stress, the decrease of I_ON could be explained by the lower hole tunneling current through the more increased Schottky-barrier height and the increased I_OFF could be explained by the increase of the amount of electron thermal emission and tunneling through thinner Schottky-barrier into the near drain. After hot carrier stress, it is observed that the threshold voltage shifts to more negative values for all stress gate voltages and the drain current is decreased. The device degradation is more significant as the stress gate voltage decreases.     

Insights on trap generation and breakdown in ultra thin SiO2 and SiON dielectrics from low voltage stress-induced leakage current measurements

We review the advancements in the understanding of breakdown and trap generation that have been achieved using low voltage stress-induced leakage current as a probe of the interface states created during electrical stress of ultra thin SiO₂ and SiON gate dielectrics. The technique separates the effects of bulk and interface states on the post-stress I–V characteristics; senses interface traps at both contact interfaces, identifies the regime where interface rather than bulk state generation is the rate limiting step for breakdown, is useful for determining the operative trap creation processes, and reveals the role of trap generation mechanism in driving which stress-induced defect controls breakdown.     

Analytical long-term NBTI recovery model with slowing diffusivity and locking effect of hydrogen considered

The NBTI degradation caused by hole trapping in gate insulator process-related preexisting traps (∆ V_HT) and in generated bulk insulator traps (∆ V_OT) can recover in several seconds (< 10 s), whereas the long-term recovery is dominated by interface trap generation (∆ V_IT). In this paper, various explanations of NBTI recovery have been reviewed and a compact analytical long-term NBTI recovery model in which the slowing down diffusivity and locking effect of H₂ are involved has been derived. The triangular diffusion profile of H₂ is approximated and the fitting coefficient ξ of slowing down diffusivity is related to the stress and recovery time. Our proposed model has been validated by the previous theories and numerical calculation. Moreover, the investigation of NBTI recovery on a 40-nm CMOS process has been experimentally carried out and the results show that our compact NBTI recovery model can describe the long-term recovery well.     

Improved reliability of large-sized a-Si thin-film-transistor by back channel treatment in H2

A hydrogen plasma treatment on the back-channel region of large-sized amorphous silicon thin film transistor (a-Si TFT) with high RF power and optimal process time of 20 s is proposed in this work to effectively reduce off current (I_off) and threshold voltage (V_th) shift under high and low electrical-field stresses. The channel width (W) of large-sized a-Si TFT is ranged from 1000 to 10,000 μm, which are comparable to the realistic TFTs used in the gate driver on array (GOA) of display. It is experimentally found that the mechanism of V_th shift (ΔV_th) after high electrical stress is dominated by the defect generation in a-Si layer rather than charge trapping in the gate insulator (GI) layer, which is different from the observation in previous literatures. It could be due to the effects of back-channel treatment (BCT). In addition, after low electrical stresses, the mechanism of ΔV_th is dominated by defect generation in a-Si layer, which is consistent with previous reports.     

A modified model for Si/SiGe MOS-gate delta-doped HEMTs

An analytical model for threshold voltage (V_th) and minimum gate voltage (V_tl) of Si/SiGe MOS-gate delta-doped HEMT is presented in this letter. The model is valid for any width of the delta-doped layer and any distance of the layer from the Si/SiO₂ interface. Using the model, V_th and V_tl of a Si/SiGe MOS-gate delta-doped HEMT of known dimensions are calculated. To investigate the effect of variation of the width of the delta-doped layer, the threshold voltage and the minimum gate voltage have been plotted against the width. Medici™ simulation have been performed on the same device to evaluate V_th and V_tl for different delta-doped layer widths. The simulation results are in good agreement with the results found using the analytical model.     

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t_ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V_th and of linear drain current I_dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V_th and I_dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO₂/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.     

Analytical parameter extraction for NBTI reaction diffusion and trapping/detrapping models

Accurate parameters of negative bias temperature instability (NBTI) model are essential to predict the circuit lifetime during circuit design. This paper presents the extraction methods of NBTI model parameters for the NBTI reaction-diffusion (R-D) and trapping/detrapping (T/D) models. The R-D model parameters extraction mainly includes two steps: linear approximation and optimized extraction. In the first step, the term of ΔV_th^1/2n is described as approximately linear with t^0.5 after the coordinate system conversion, where ΔV_th is the degradation in threshold voltage and t is elapsing time. Then, the model parameters can be roughly calculated. In the second, an objective function of the genetic algorithm (GA) has been built up and its constraints can be determined by referring the values gotten from the first step. After solving the function, a set of accurate parameters of the NBTI model can be achieved. Similarly, the T/D model parameters extraction involves the curves fitting and further optimization based on the GA. Both the R-D and T-D extraction methods have been validated using a 40-nm CMOS process, and it is easy to implement the extraction procedures in a program extractor.     

A simplified model for the static characteristics of amorphous silicon thin-film transistors

A simplified and more accurate expression for the static I_D − V_D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT) has been derived. The results show that the experimental drain characteristics agree very well with the derived equations. This model shows its greatest improvement over other models at low values of gate voltage and at large values of drain voltage. The model is based on the experimental function for the channel conductance vs gate voltage. Four constants, obtained from the experimental data of I_D vs V_G at some small value of V_D, are used to completely specify the simplified model. The theoretical results confirm the simple form of the model in terms of the device geometry. The constants calculated from the theory agree well with those extracted from the conductance data.     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

Controllable threshold voltage of a pentacene field-effect transistor based on a double-dielectric structure

The authors report controllable threshold voltage (V_th) in a pentacene field-effect transistor based on a double-dielectric structure of poly(perfluoroalkenyl vinyl ether) (CYTOP) and SiO₂. When a positive switching voltage is applied to the gate electrode of the transistor, electrons traverse through the pentacene and CYTOP layers and subsequently trapped at the CYTOP/SiO₂ interface. The trapped electrons induce accumulation of additional holes in the pentacene conducting channel, resulting in a large V_th shift from ?4.4 to +4.6 V. By applying a negative switching voltage, the trapped electrons are removed from the CYTOP/SiO₂ interface, resulting in V_th returning to an initial value. The V_th shift caused by this floating gate-like effect is reversible and very time-stable allowing the transistor to be applicable to a nonvolatile memory that has excellent retention stability of stored data.     

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiO _x -cladded Si or GeO _x -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiO _x -cladded Si and GeO _x -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO₂ tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I _D–V _G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.