Characterization of direct patterned Ag circuits for RF application

We investigated the effects of sintering temperature on microstructural evolution and electrical characteristics of screen printed Ag patterns. A commercial conducting paste containing Ag nanoparticles was screen printed onto a Si substrate passivated with SiO₂ and sintered under a sintering temperature range from 150 °C to 300 °C. Four point probe method was used to measure the DC resistance, while a network analyzer and Cascade’s probe system in the frequency range from 10 MHz to 30 GHz were employed to measure the S-parameters of the sintered Ag conducting patterns. The resistivity under the application of a DC decreased from 398 μΩ cm to 9 μΩ cm with increasing sintering temperature from 150 °C to 300 °C. From the measured S-parameters, the electrical losses in high frequencies also decreased with increasing sintering temperature (about 1.2 dB at 30 GHz) due to the formation of an interparticle neck after heat treatment at high temperatures.     

Surface acoustic wave characteristics of AlN thin films grown on a polycrystalline 3C-SiC buffer layer

In this study, AlN thin films were deposited on a polycrystalline (poly) 3C-SiC buffer layer for surface acoustic wave (SAW) applications using a pulsed reactive magnetron sputtering system. AFM, XRD and FT-IR were used to analyze structural properties and the morphology of the AlN/3C-SiC thin film. Suitability of the film in SAW applications was investigated by comparing the SAW characteristics of an interdigital transducer (IDT)/AlN/3C-SiC structure with the IDT/AlN/Si structure at 160 MHz in the temperature range 30-150 °C. These experimental results showed that AlN films on the poly (1 1 1) preferred 3C-SiC have dominant c-axis orientation. Furthermore, the film showed improved temperature stability for the SAW device, TCF = −18 ppm/°C. The change in resonance frequency according to temperature was nearly linear. The insertion loss decrease was about 0.033 dB/°C. However, some defects existed in the film, which caused a slight reduction in SAW velocity.     

Microvaristors in thick-film and LTCC circuits

ZnO-based varistors protect electronic circuits against overvoltage. High temperature from the range of 1150-1300 °C is required for proper sintering of such material. Varistor inks with lower firing temperature are needed for application in thick-film and LTCC technology. ZnO-based thick-film composition was prepared and varistors were fabricated on alumina and LTCC substrate. Different topologies (capacitor-like or planar), electrode metallurgies (PdAg, Au or Pt-based) and firing profiles (850 °C or 950 °C) were used. Samples microstructure was investigated. Varistor I-V characteristics, long-term stability and durability to high voltage pulses were examined. Satisfactory results were achieved, because nonlinearity coefficient α up to 23 was obtained for capacitor-like varistors with Pt terminations on LTCC substrates, long-term thermally aged (150 h at 250 °C) varistors had slightly smaller nonlinearity coefficient and characteristic voltage, V_1 mA and components subjected to series of high voltage pulse (1000 pulses with 10 mA amplitude and 5 ms duration each) exhibited almost the same electrical parameters.     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

Evaluation of a novel unfluorinated copper precursor for chemical vapor deposition

A kinetics of the chemical vapor deposition (CVD) of copper using novel unfluorinated precursor, copper(I)(N(1(dimethylvinylsiloxy)-1-methylethano)-2-imino-4-pentanoate), namely Cu-KI5, was studied. Since its great thermal stability, Cu-KI5 allowed high source temperature to provide high vapor pressure, for example Cu-KI5 has a vapor pressure of 0.2-2.2 Torr at the temperature range of 100-140 °C. Furthermore, copper could be deposited by direct reduction from Cu-KI5 instead of disproportionation. By using formic acid (HCOOH) as a reducing agent, copper films were deposited on ruthenium substrate at temperature range of 150-350 °C. The activation energy was 48.9 kJ/mol in surface reaction limited region (<210 °C) and 1.9 kJ/mol in diffusion limited region (>210 °C) at the total pressure of 5 Torr. Secondary ion mass spectroscopy (SIMS) analysis showed that CVD copper film of high purity (>99.99%) was deposited at 250 °C. The as-deposited copper films grown at 150-300 °C exhibited strong 〈111〉 preferred orientation. The minimum resistivity of the copper film was 1.77 μΩ cm obtained at the deposition temperature of 250 °C. In the surface reaction limited region, kinetic data extracted from experiments enabled 2-D computational simulation to predict copper deposition into trench structures. Simulation results showed excellent step coverage, which was larger than 90% for aspect ratio of 10:1. Cu-KI5 is a promising Cu-CVD precursor for the fabrication of ultra large scale integration (ULSI) or through silicon via (TSV) copper interconnects.     

Investigation and simulation on the dynamic shock response performance of packaged high-g MEMS accelerometer versus the impurity concentration of the piezoresistor

To enhance the stability of packaged high-g MEMS accelerometers with double cantilevers positioned asymmetrically, the dynamic shock responses of components versus impurity concentration of piezoresistors at various working temperatures have been probed by using Finite Element Method (FEM). Results indicate that the dynamic output responses of component are actually the superposition of the forced vibrations with dynamic shock and those of cantilevers in their eigenfrequency. The dynamic responses of components are sensitive to the working temperature. With the increase of working temperature, the inherent frequency vibrations of the cantilevers are depressed gradually. Moreover, the larger the difference between the working temperature and reference temperature, the more obvious the impurity effect of piezoresistors is. The difference between the peak output voltage of response under 1 × 10¹⁸ cm⁻³ and that under 1 × 10²¹ cm⁻³ varies greatly from −2.2146 mV at T = 0 °C to 8.6609 mV at T = 100 °C, of course, is partly due to the characteristic variation of damping media under various working temperatures. Therefore, to improve the stability of component and further weaken the impurity concentration effect and the temperature effect of piezoresistors on the performance of components, it is necessary to increase the impurity concentration of piezoresistors and keep the components working at relatively lower temperature only if the electro-performance of component is satisfied.     

Surface acoustic wave characteristics of ZnO films grown on a polycrystalline 3C-SiC buffer layer

Zinc oxide (ZnO) thin films were deposited onto a polycrystalline (poly) 3C-SiC buffer layer for surface acoustic wave (SAW) applications using a magnetron sputtering system. Atomic force microscopy (AFM) and X-ray diffraction (XRD) showed that the ZnO grown on 3C-SiC/Si had a smooth surface, a dominant c-axis orientation and a lower residual stress in ZnO thin film compared to that grown directly onto Si substrate. In order to evaluate the SAW characteristics of ZnO films on a 3C-SiC buffer layer, the two-port SAW resonators, based on inter-digital transducer (IDT)/ZnO/3C-SiC/Si and IDT/ZnO/Si structures, were fabricated and measured within a temperature range of 25-135 °C. The resulting 3C-SiC buffer layer improved the insertion loss by approximately 7.3 dB within the SAW resonator and enhanced the temperature stability with TCF = −22 ppm/°C up to 135 °C in comparison to that of TCF = −45 ppm/°C within a temperature range of 25-115 °C of the ZnO/Si structure.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C (after individual resistor trimming) for the −20 to +80 °C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.     

Risk of whiskers formation on the surface of commercially available tin-rich alloys under thermal shocks

Tin whiskers can be dangerous for circuit reliability because of short circuits or device littering. This article presents the results of the studies of whisker formation, after 1500 shocks at the cyclic temperature range of −45 °C to +85 °C, growing on the surface of the commercially available tin-rich materials and alloys used in electronics i.e. pure tin (Sn100), Sn96.5Ag3Cu0.5 and Sn99Ag0.3CuNiGe.     

Fabrication of quasi-one dimension silicon carbide nanorods prepared by RF sputtering

Anodic aluminum oxide (AAO) template was prepared by a two-step anodization method at low temperature (1 °C) and silicon carbide was deposited on the templates by non-reactive radio frequency sputtering method. Well-aligned quasi-one dimension silicon carbide nanorods with the average diameter about 80-90 nm and a mean length of 400 nm were obtained perpendicular to the substrate and observed by AFM and SEM after the aluminum substrates were striped off. Then some samples were annealing at flowing N₂ at 400, 500 and 600 °C and FTIR was performed on these samples to obtain the information of structure.     

A CMOS piecewise curvature-compensated voltage reference

This paper presents a novel approach to the design of a high-precision CMOS voltage reference. The proposed circuit utilizes MOS transistors instead of bipolar transistors to generate positive and negative temperature coefficient (TC) currents summed up to a resistive load to generate low TC reference voltage. A piecewise curvature-compensation technique is also used to reduce the TC of the reference voltage within a wider temperature range. The output reference voltage can be adjusted in a wide range according to different system requirements by setting different parameters such as resistors and transistor aspect ratios. The proposed circuit is designed for TSMC 0.6 μm standard CMOS process. Spectre-based simulations demonstrate that the TC of the reference voltage is 4.3 ppm/°C with compensation compared with 107 ppm/°C without compensation in the temperature ranges from −15 to 95 °C using a 1.5 V supply voltage.     

Impact of the CMP process on the electrical properties of ultra low k porous SiOCH

The impact of chemical mechanical polishing (CMP) on SiOCH films (thickness = 300 nm) for the 32-45 nm node Cu-interconnect process is investigated by low-frequency dielectric spectroscopy and thermally stimulated depolarization current (TSDC). After CMP process, the dielectric permittivity is degraded of about 25% in the whole range of the investigated frequency (10⁻¹ Hz-100 kHz). In a same way, the dielectric losses tan δ increase at the lowest frequencies. An annealing (300 °C during 20 min) carried out after CMP induces a reduction of the dielectric permittivity without however reaching the value of initial as-deposited material. In agreement with other published papers focusing on the damage caused by the CMP, OH bonding and water adsorption due to surfactants explain the degradation of these dielectric properties. The identification of OH bonds and an increase in the intensity of CH_x in the 2800-3050 cm⁻¹ range after CMP seems to confirm this point. The moderate temperature of annealing, used to restore layers and to avoid the degradation of copper lines, suppresses the physisorbed water but not the chemisorbed water. TSDC measurements confirm that dipolar relaxation, due to water in the material, result in a peak of relaxation at a temperature around 175 °C.     

Visible photoluminescence from Ge nanoclusters implanted in nanoporous aluminum oxide films

Nanoporous aluminum oxide (Al₂O₃) films with uniform porous size of 45 nm prepared by the electrochemical process in inorganic acid medium were implanted at room temperature (RT) with 120 keV Ge⁺ ions with a fluence of 1.2×10¹⁶ cm⁻². The nucleation and growths of Ge nanoparticles, were obtained by thermal annealing of the implanted samples at the temperature range of 200-600 °C. The size and distribution of the nanoparticles were characterized by photoluminescence (PL) measurements. The photoluminescence measurements as a function of the annealing temperature shows that at low annealing temperature (200 °C), the sample presents a low intensity and broad emission band centered at 5456 Å consistent with emission band characteristics of nanocluster of Ge with diameter in the range of 4-8 nm, as the annealing temperature increases to 400 °C the PL intensity increases by a factor of almost 20 and the emission band suffers a small red shift. The intensity increases can be related to the increase of the number of Ge nanocluster. At the annealing temperature of 600 °C, the emission band is considerably red shifted by almost 172 Å and the emission intensity decreases significantly, strongly suggesting that nanocrystalline Ge having a character of direct optical transitions exhibits the visible photoluminescence.     

Generating sub-1V reference voltages from a resistorless CMOS bandgap reference circuit by using a piecewise curvature temperature compensation technique

A piecewise curvature compensated CMOS voltage reference that is able to generate a sub-1V reference voltage is presented. The presented voltage reference circuit is operated at a minimum operating voltage of 1.5 V (theoretically 1.408 V) and generates a stable 0.658 V reference voltage with a temperature coefficient of 9.617 ppm/°C over the temperature range of −10 °C to 130 °C. When implemented in a 0.18 μm CMOS technology, the presented design occupies a compact silicon area of 0.022 mm². Spectre SPICE simulation showed that the presented design achieves a line regulation of 0.89%, a power supply rejection ratio of −42.3 dB, a power consumption of 0.449 mW at 1.8 V power supply and a high immunity to process variation.     

Structure and property of magnetron sputtered ternary cobalt-nickel silicide films

Ternary cobalt-nickel silicide films were prepared using magnetron sputtering from an equiatomic cobalt-nickel alloy target on Si substrate. The effect of post-deposition annealing on the phase formation, structural properties and resistivity of the resultant films has been studied. The results of XRD show that the annealing temperature and impurity level of oxygen play a crucial role in controlling the phase transformation of ternary silicide. Silicide phases are absent in the as-deposited film due to the amorphous nature. At relatively low annealing temperature, the phase of CoNi₃Si (2 2 0) and CoNiSi (2 2 0) coexist. With the increase of annealing temperature, the phase of CoNi₃Si (2 2 0) begins to transform into CoNiSi (2 2 0). At high annealing temperature (800 °C), only the phase of CoNiSi₂ (2 2 2) is formed. For Co-Ni silicide film annealed in pure argon gas ambient, two Raman peaks at 1357 cm⁻¹ and 1591 cm⁻¹ are attributed to the vibrational mode of CoSi₂ and NiSi₂ compounds. For ternary silicide annealed in atmosphere ambient, two Raman peaks located at 538 cm⁻¹ and 690 cm⁻¹ were observed and may be related to Si oxide or Co-Ni oxide. The 3D views of AFM images show that the surface roughness is relatively low when the silicidation temperature is smaller than 550 °C. After silicidation in 800 °C, the surface roughness increases abruptly. The resistance initially decreases with the increase of annealing temperature, and achieves minimum value (19 μΩ cm) in temperature ranges 500-550 °C. When the annealing temperature increases from 600 °C to 800 °C, the resistivity was found to increase slightly to 26 μΩ cm. The ternary silicide shows a temperature window for low resistivity as compared to binary NiSi.     

Measurements of charge carrier mobilities and drift velocity saturation in bulk silicon of 〈1 1 1〉 and 〈1 0 0〉 crystal orientation at high electric fields

The mobility of electrons and holes in silicon depends on many parameters. Two of them are the electric field and the temperature. It has been observed previously that the mobility in the transition region between ohmic transport and saturation velocities is a function of the orientation of the crystal lattice.This paper presents a new set of parameters for the mobility as function of temperature and electric field for 〈1 1 1〉 and 〈1 0 0〉 crystal orientation. These parameters are derived from time of flight measurements of drifting charge carriers in planar p⁺nn⁺ diodes in the temperature range between −30 °C and 50 °C and electric fields of 2 × 10³ V/cm to 2 × 10⁴ V/cm.     

The evolution of microstructure and microhardness of Sn-Ag and Sn-Cu solders during high temperature aging

The changes in microstructure and microhardness of Sn-0.5Ag, Sn-1.0Ag, and Sn-0.7Cu Pb-free solders were investigated during high temperature aging at 200 °C. As-solidified microstructures, revealed by cross-polarized light microscopy, consist of relatively large Sn grains in both Sn-Ag and Sn-Cu solders. Upon aging at 200 °C, 2 h, Sn grains become smaller compared to the as-solidified ones. In addition, the microhardness of Sn-Ag solders increases after 200 °C, 2 h aging, while that of Sn-Cu solder decreases. Detailed observation of the coarsening and redistribution of intermetallic particles in each system further explains this response of mechanical properties during high temperature aging. To investigate the effect of aging temperature, solders were aged at a lower temperature, 150 °C for up to 1000 h and compared with aging at 200 °C. The microstructural changes during the high temperature aging were characterized in terms of Sn grain size, crystal orientation, and IMC growth kinetics, and were further correlated with the changes of their mechanical properties.     

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4 at.%)/Si(1 0 0) and Ni_0.6Si_0.4(Pt 4 at.%)/Si(1 0 0) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni_0.6Si_0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N₂ environment in a temperature range from 200 to 900 °C for 2 min. The samples were analyzed by four point probe sheet resistance (R_s) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700 °C. Instead, for the Ni_0.6Si_0.4(Pt)/Si structure, 100 °C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4 at.%)/Si(1 0 0) structure. XRD, AFM and R_s analyses confirmed formation of a continuous NiSi film with R_s value of 5 Ω/□ in a temperature range of 700−800 °C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.     

Influence of mechanical stress on adhesion properties of DC magnetron sputtered Ti/NiV/Ag layers on nSi substrate

Due to insufficient adhesion of sputtered Ti/NiV/Ag metallization scheme on n⁺Si substrate when annealed below 550 °C, investigation was focused on the influence of process parameters on adhesion properties. Adhesion between metallic stack and Si substrate was found to be a strong function of annealing temperature. Additional investigations showed that the cause for poor adhesion was also rather high residual stress in metal thin layers, particularly stress in sputtered NiV layer. High residual stress was measured for NiV (1883 ± 252 MPa) and lower for Ti (334 ± 60 MPa) and Ag (310 ± 10 MPa) layer, respectively. The influence of sputtering parameters on the stress behavior was experimentally verified. By reducing the cathode DC power and Ar working pressure during NiV sputtering we were able to reduce the stress within the structure. A clear correlation was found between the residual stress magnitude and adhesion properties within the temperature range from room temperature to 550 °C. By residual stress reduction within a metallic stack, the necessary annealing temperature to obtain optimal adhesion was reduced from 550 to 500 °C.