A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

正The double gate(DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design.To develop a physical model for extremely scaled DG MOSFETs,the drain current in the channel must be accurately determined under the application of drain and gate voltages.However,modeling the transport mechanism forthe nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time(self-consistent,quantum computations,...). Therefore,new methods and techniques are required to overcome these constraints.In this paper,a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs.The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design.The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.     

Efficient logic architectures for CMOL nanoelectronic circuits

CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. Two new CMOL building blocks using transmission gates have been introduced to obtain efficient combinational and sequential logic for CMOL designs. Compared with the existing CMOL circuits, the proposed CMOL designs based on these blocks can achieve more than 30% improvement in speed and up to 80% improvement in density and power consumption while providing similar fault tolerance capabilities. This work significantly advances the applications of CMOL to actual electronic circuits and systems     

电子政府网络架构设计综合解决方案

电子政府（E-goverment,E-gov）网络架构可分为中央城域网、省域城域网、市级城域网以及县域城域网4层。以东非某国电子政府E-gov网络建设为例,系统介绍E-gov网络架构设计的综合解决方案。首先,详细介绍E-gov网络建设所涉及到的IP 数据网络设计和设备选型,无线网络和有线宽带传输中的VPN设计,以及网络安全可靠和云特性等;其次,论述E-gov系统数据中心架构设计;最后,对E-gov网络系统中的上层业务应用网络架构（UC,E-mail,VC,UP等）的设计进行阐述。     

一种安全数据库体系结构的设计

较为详细地分析了安全数据库实现的模型和技术，重点论述了多级安全数据库中的强制访问控制和基于角色的访问控制模块的实现方案及其关键技术；并在此基础上设计出了一种安全级别至少为Bl的安全数据库体系结构。     

A three-terminal planar selfgating device for nanoelectronic applications

We report on a new nanoelectronic planar three-terminal device, fabricated from III/V semiconductor-based heterosystems. Utilizing the benefits of selfgating and in-plane gates, the tunable three-terminal device presented exhibits strong non-linear input- and transfer-characteristics, both, at liquid Helium and at room temperature. For a given side-gate voltage, the devices input characteristics closely resemble that of a conventional diode, although it is fabricated by a single post-growth patterning process only, i.e., etching of deep trenches. We present a simple model, based on an equivalent circuit, which well reproduces the experimental findings. Possible applications are discussed.     

Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems

In this paper, a learnable cellular nonlinear network (CNN) with space-variant templates, ratio memory (RM), and modified Hebbian learning algorithm is proposed and analyzed. By integrating both the modified Hebbian learning algorithm with the self-feedback function and a ratio memory into CNN architecture, the resultant ratio-memory (RMCNN) is called the self-feedback RMCNN (SRMCNN) which can serve as the associative memory. It can generate the absolute weights and then transform them into the ratioed A-template weights as the ratio memories for recognizing noisy input patterns. Simulation results have shown that with the stronger feature enhancement effect, the SRMCNN under constant leakage current can store and recognize more patterns than the RMCNN. For 18 /spl times/ 18 SRMCNN, 93 noisy patterns with a uniform distribution noise level of 0.8 and a variance of normal distribution noise of 0.3 can be learned, stored, and recognized with 100% success rate. The SRMCNN has greater learning and recognition capability when the learned patterns are simpler and the noise is lower. For the learning and recognition of complicated patterns, the allowable pattern number is decreased for a 100% success rate. Simulation results have successfully verified the correct functions and better performance of SRMCNN in the pattern recognition. With high integration capability and excellent pattern association performance, the proposed SRMCNN can be applied to nanoelectronic associative-memory systems for image processing applications.     

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFETfor nanoelectronic circuit design

The double gate (DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time (self-consistent, quantum computations, ...). Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design. The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.     

纳米电子技术在军事领域的应用

详细阐述了纳米电子技术及微机电技术在军事计算机、微小卫星、飞机侦察和干扰、导航制导、武器装备、单兵系统等军事领域的应用前景。介绍了部分军事强国在纳米科技领域的发展和部署状况,分析了我国纳米科技和纳米电子技术的发展现状,并指出发展纳米科技和纳米电子技术对占领未来电子信息战制高点具有战略意义。     

无线传感器网络的轻量级安全体系研究

结合无线传感器网络现有的安全方案存在密钥管理和安全认证效率低等问题的特点,提出了无线传感器网络的轻量级安全体系和安全算法。采用门限秘密共享机制的思想解决了无线传感器网络组网中遭遇恶意节点的问题;采用轻量化ECC算法改造传统ECC算法,优化基于ECC的CPK体制的思想,在无需第三方认证中心CA的参与下,可减少认证过程中的计算开销和通信开销,密钥管理适应无线传感器网络的资源受限和传输能耗相当于计算能耗千倍等特点,安全性依赖于椭圆离散对数的指数级分解计算复杂度;并采用双向认证的方式改造,保证普通节点与簇头节点间的通信安全,抵御中间人攻击。     

An architecture design approach for large satellite networks

Designing a world-wide satellite network that consists of hundreds of user sites and thousands of circuit connections is a complex problem, which involves selecting a set of candidate satellites and satellite beams/frequency bands from among numerous existing and planned satellites, evaluation of circuit connectivity, earth-station compatibility and sizing, and estimating transponder loading. The design process may also require assessment of the impact of a different set of satellites and modified user traffic requirements on the space segment, the earth-station types and quantity, and the total system cost. Although a conventional design approach based on link-by-link and site-by-site analysis provides accurate results, it is time-consuming and impractical for developing high-level network architectures in a time-constrained environment. A design technique is proposed which employs a set of rules for satellite network design, in combination with extensive databases of satellite parameters, earth-station parameters and user traffic requirements, to synthesize a network architecture. The technique is particularly useful for performing high-level trade-offs among alternative architectures in terms of space segment requirements, the number and type of earth-stations and overall system cost. Once the desired architecture has been selected, a detailed design may be developed using conventional methods.     

开放式机载时间同步系统的架构设计

针对现有机载时间同步系统在综合航电系统架构下通用性和可扩展性不足的问题,提出了一种具有开放式特征的机载时间同步系统架构。首先根据机载时间同步系统应用需求,分析了机载平台可选的技术手段,然后围绕时间链路、时间处理、时间管理、时间应用等基本要素,将机载时间同步系统自上而下划分为三个部分,从而形成分层次的机载时间同步架构。该架构在层间采用了标准开放接口,能同时兼容多种机间时间比对链路,具备多时间管理和时间品质评估的能力。最后,介绍了该架构下的时间同步实现流程,并分析了影响同步精度的主要误差环节。桌面测试结果表明,所提架构能够实现优于10 ns的时间同步精度。     

P2P网络架构的资源搜寻算法设计

结构化对等(P2P,Peer to Peer)架构的资源搜寻算法如Chord、CAN、Pastry等的提出,改变了非结构化P2P架构的泛洪式资源搜寻的方式,降低了P2P资源搜寻信息的流量,从而增强了系统的扩展性.但是以上算法均未考虑到节点间实际物理距离对搜寻路径长度的影响.文章提出一种基于节点能力和节点区域性的结构化搜寻算法,该算法综合了CBT和Grapes的优点并充分考虑到节点的区域性以及节点能力,从而构建了一个短搜寻路径能力集包容的P2P系统.     

Communication architecture design for reconfigurable multimedia SoC platform

Memory and communication architecture have a significant impact on the performance, cost, and power of complex multiprocessor system-on-chip designs. In this paper, we present an automated bus matrix synthesis flow for efficient transaction-level design space exploration of communication architecture in a reconfigurable multimedia system-on-chip platform. Specifically, we consider hardware interface selection problem, which has significant effect on the overall cost of area and power. We propose a method to solve such hardware interface selection problem through static analysis of communication behavior. We experiment with JPEG encoder and H.264 encoder examples and the results show the reduction of area by 56.91% and power by 48.61% of bus matrix with 0.58% performance overhead on average compared to the case of maximum performance. According to our HW interface selection algorithm, we also experiment MPEG4 video decoder example. And the result is evaluated on the FPGA prototyping board.     

A systolic architecture for optimal filter design support

A prototype filter design is reviewed to underscore the computational problems arising in such designs. A purely systolic-array architecture is presented. This array provides the computational support necessary for filter design. Due to a simple and novel data steering technique the array is capable of carrying out a number of important matrix operations such as factorization, inversion of factors, and matrix-matrix multiplication. Another interesting attribute is the array's ability to maximally overlap computations of multiphase algorithms. In this study we demonstrate the execution of a dense matrix factorization phase and a factor inversion phase on the array with no need for intraphase or interphase I/O. We show that these phases (which are the backbone of an optimal filtering algorithm) are completed in the optimal count of aboutn time units. The array employs 2n ⁿ–n simple processing elements (PEs) that are active every other time unit. It is shown that the functions of two adjacent PEs can be merged and assigned to a single PE thus maximizing PE utilization. A possible design of a merged PE is given.     

Cell hopping: a lightweight architecture for wireless communications

We propose a novel lightweight cellular wireless network architecture called cell hopping. Unlike traditional cellular networks, cell hopping has base stations interconnected by wireless inter-base station links, WIBLs. WIBLs support all routing and switching in cell hopping networks, obviating the need for costly core networks (or a costly switching infrastructure). Cell hopping utilizes an unlicensed frequency and presents a low-cost, rapidly deployable solution for mobile communications. We discuss various technical challenges that must be addressed before cell hopping can become a reality. In particular, we concentrate on location management. We propose an on-demand location management technique that completely eliminates the need for location databases and periodic updates by mobile stations. We provide a few variations of the location management scheme, and compare their performance through simulation.     

A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization.In the present paper,a new approach for modeling semiconductor devices,nanoscale double gate DG MOSFETs,by use of the gradual channel approximation(GC) approach and genetic algorithm optimization technique(GA) is presented.The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction,to achieve reliable,accurate and simple compact models for nanoelectronic circuit simulations.Our compact models give good predictions of the quantum capacitance,threshold voltage shift,quantum inversion charge density and drain current.These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrodinger equations.The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.     

MPEG-4运动补偿的VLSI结构设计

针对MPEG．4解码中运动补偿控制复杂、数据吞吐量大、实现较困难，提出了一种适合MPEG-4的运动补偿硬件实现方案，解决了时序分配、输入输出控制等较难处理的问题。此方案已经在Xilinx ISE6．li集成开发环境下，采用了VHDL进行描述，并使用了电子设计自动化（EDA）工具进行了模拟和验证。仿真和综合结果表明，设计的运动补偿处理器逻辑功能完全正确，而且可以满足MPEG-4 Core Profiles ＆ Level 2的实时编码要求，可用于MPEG-4的VLSI实现。     

Simplified biorthogonal discrete wavelet transform for VLSI architecture design

Biorthogonal discrete wavelet transform (BDWT) has gained general acceptance as an image processing tool. For example, the JPEG2000 standard is completely based on the BDWT. In BDWT, the scaling (low-pass) and wavelet (high-pass) filters are symmetric and linear phase. In this work we show that by using a specific sign modulator the BDWT filter bank can be realized by only two biorthogonal filters. The analysis and synthesis parts use the same scaling and wavelet filters, which simplifies especially VLSI designs of the biorthogonal DWT/IDWT transceiver units. Utilizing the symmetry of the scaling and the wavelet filters we introduce a fast convolution algorithm for implementation of the filter modules. In multiplexer–demultiplexer VLSI applications both functions can be constructed via two running BDWT filters and the sign modulator. This work was supported by the National Technology Agency of Finland (TEKES).