Forward error correcting codes in synchronous fiber optictransmission systems

This paper proposes forward error correcting (FEC) code for synchronous digital hierarchy (SDH) fiber optical transmission systems. They are (18880, 18865) and (2370, 2358) shortened Hamming codes and are encoded at the multiplex-section layer; the check bits are embedded in auxiliary multiplex-section overhead (MSOH) bytes. The codes realize general circuit configurations regardless of the transmission speed or path-size, perfect compatibility with SDH format, suppressed processing delay accumulation, and decrease the chance of line-switching in the case of signal degradation. To ensure that the various requirements of each network-provider such as customized usage of SOH bytes and affordable circuit scale could be satisfied, a trial circuit board was constructed on the programmable hardware called PROTEUS, which enables flexible operation in terms of code-selection and check bit area. We actually confirm error-correcting capability through the first STM-64 FEC-coded-optical transmission experiment. The statistics of error occurrence in the optical transmission line are also studied. The result indicates that the proposed codes are effective in optical transmission systems if the BER is limited by optical noise and dispersion     

A ranked order filter implementation for parallel analog processing

Order statistic filtering, the generalization of which is ranked order filtering, is needed for many image-processing functions including median filtering and mathematical morphology. Combining order statistic functionality with the parallel operation and local connectivity of array processing approaches such as the cellular nonlinear network model, has the potential for very high performance in image processing. This paper examines the implementation of programmable ranked order extraction with a very compact hardware realization of an analog current-mode ranked order filter. The considerable savings in the required circuit area, compared to other circuits, make it possible to use the structure as a building block in a massively parallel signal processing array. The operation of the circuit is analyzed in detail with the help of simulations and measurement results obtained from a test chip manufactured in a 0.18-/spl mu/m standard digital CMOS technology are also presented. The simulations and measurement results verify the correct operation of the circuit and show that it is very suitable for inclusion in every cell of a large parallel processor array. This makes many grayscale processing functions available with truly parallel operation and therefore very high performance.     

双口RAM在图像处理系统中的应用研究

基于图像处理系统实时性和大数据量冲突的问题,提出了在图像处理系统中使用双口RAM的方法。介绍了双口RAM的功能和特点,以IDT70V09芯片为例给出了图像处理系统中应用双口RAM的系统架构设计、硬件接口设计、系统软件设计以及FPGA和DSP对双口RAM操作软件的详细设计,并针对双口RAM的端口争用问题与解决方法进行了详细讨论,对系统的印制板设计和电路调试提出了建议。最后对图像处理系统进了功能测试,证明了采用双口RAM设计的系统的稳定性和可行性。     

Microelectronics for dynamic neural networks

Artificial Neural Networks are the massively parallel interconnection of simple processing elements. Computing times for the simulation of these parallel systems on today’s von-Neumann-computers increase with the squared number of processing elements. There is a need for application specific hardware. This paper describes various investigations of analog as well as digital hardware for neural networks. Possible solutions for the connection problem and different circuit designs will be explained. Then our cascadable digital circuit for the emulation of a biology-oriented, dynamic neural network will be presented.     

Frequency-locked loop circuit providing large pull-in range

Presents a frequency-locking circuit that provides a larger pull-in bandwidth than that of a conventional automatic frequency control (AFC) circuit. In addition, the proposed circuit has a stable mode of operation over the full frequency response of the frequency discriminator, and locks the oscillator at exactly the centre frequency of this discriminator. The frequency offset and the unstable mode of operation presented by the conventional circuit outside its pull-in range can thus be eliminated.<>     

A charge-based neural Hamming classifier

A charge-based fixed-weight neural Hamming classifier with an on-chip normalization facility is described. The classifier utilizes a purely capacitive synapse matrix for quantization and a multiport sense amplifier for discrimination. The discriminator is compatible with variable-weight synapses as well. A detailed analysis of the classifier configuration is presented; design issues are addressed, and limitations are identified. It is shown that the ratio of the maximum Hamming weight to the minimum Hamming distance that can be handled by the classifier has an upper bound. As long as the exemplars comply with this upper bound, the network does not impose any limitation on the word length. A very large exemplar count, on the other hand, can impair connection density, but this problem can be averted by using multiple discriminators. A 2-μm p-well CMOS test chip containing a Hamming classifier of ten 20-b-long exemplars is described     

Compressive Receiver Using a CRLH-Based Dispersive Delay Line for Analog Signal Processing

A compressive receiver (CR) is presented utilizing a composite right/left-handed (CRLH) dispersive delay line (DDL) for analog signal processing applications. The CRLH DDL offers advantages such as arbitrary frequency of operation and wide bandwidth, filling a gap with competing DDL technologies. The presented CR system utilizes an impulse-driven CRLH DDL and mixer inversion for chirp generation required for real-time signal processing. At high frequencies, this eliminates frequency ramp generators. The CR is employed as a frequency discriminator and a tunable delay line with dispersion compensation. The simulation and experimental results fully validate the presented systems as proof-of-concept for high-frequency applications such as real-time Fourier transformers and signal analyzers.      

基于细胞神经网络的从阴影恢复形状的新方法

细胞神经网络(CNN)是一种实时处理信号的大规模非线性模拟电路,它的连续时间特点以及局部互连特点使其可以进行并行计算,并且非常适用于超大规模集成电路(VLSI)的实现.本文针对从阴影恢复形状(SFS)问题,提出了一种基于硬件退火CNN的能量函数优化方法,并对该方法进行了详细分析,给出了实例的仿真结果,验证了该方法的有效性.该方法为并行处理算法,具有运算量小、易于大规模VLSI集成实现,且能够克服局部极小等优点,可以使SFS问题得到实时的处理.     

基于运动目标的二维时间延迟积分红外图像增强

在探讨二维时间延迟积分等红外图像增强技术的基础上,特别针对目标以较大速度运动的情况,提出一种将二维时间延迟积分与目标运动特性相结合的运动运动自适应红外图像增强算法,同时,从系统硬件实时化处理的目的出发,给出了硬件实现方法与具体实验结果,从实验结果看出,所设计系统在图像增强的同时,很好地消除了因目标运动带来的模糊效应.     

Image guidance of endovascular interventions on a clinical MRscanner

Magnetic resonance imaging (MRI) offers potential advantages over conventional X-ray techniques for guiding and evaluating vascular interventions. Image guidance of such interventions via passive catheter tracking requires real-time image processing. Commercially available MR scanners currently do not provide this functionality. This paper describes an image processing environment that allows near-real-time MR-guided vascular interventions. It demonstrates (1) that flexibility can be achieved by separating the scanner and the image processing/display system, thereby preserving the stability of the scanner and (2) that sufficiently rapid visualization can be achieved by low-cost workstations equipped with graphics hardware. The setup of the hardware and the software is described in detail. Furthermore, image processing techniques are presented for guiding the interventionalist through simple vascular anatomy. Finally, results of a phantom balloon angioplasty experiment are presented     

Extended Hamming and BCH soft decision decoders for mobile dataapplications

A methodology is presented for the design and development of efficient trellis-based soft decision decoders for extended Hamming and BCH codes. A new metric for noncoherent discriminator detection is proposed that substantially improves the performance of trellis-based decoders over additive white Gaussian noise (AWGN) channels. Minimal edge trellises are then presented for the class of extended Hamming codes and the (32, 21) extended BCH code. The latter is in extensive use in narrow-band wireless data systems. An automatic request (ARQ) protocol is described that allows the soft decision decoders to outperform their hard decision counterparts in both reliability and throughput     

Analogue VLSI morphological image processing circuit

An analogue VLSI circuit that performs morphological image processing operations on the focal plane is presented. The circuit has been fabricated using a standard digital CMOS process. We exploit the parallelism of morphological image processing operations by using the massively parallel architecture of analogue VLSI arrays, achieving both high-speed and low-power computation. The analogue circuit presented computes the grey-scale morphological operation of dilation. This system also allows for programmability of the structuring element used in the dilation operation     

SIMD技术在数字图像处理中的应用研究

SIMD处理机特别适合于要求大量高速向量或矩阵计算的场合,数据缓存系统和对准网络是它的关键部件。而图像卷积是图像处理技术中最基本也是最重要的一项技术,本文根据数字图像的卷积定理对数字图像的卷积运算进行了分析,并提出了一种基于SIMD处理机的可变卷积模板的图像卷积处理器的体系结构。该处理器内部包含有接口部件、控制部件、数据缓存系统、对准电路和执行部件等。它的极高效率的数据缓存系统和对准电路成为该处理器最有特色的部分,它从根本上解决了图像卷积中的数据复用带来的CPU重复访问主存储器的问题。实现了卷积模板为3×3的图像卷积运算,从而实现了对卷积计算的硬件加速目的。最后,对这个图像卷积处理器体系结构的性能及其可扩展性进行了缜密的分析。     

基于DSP和FPGA的高光谱图像处理系统设计

针对高光谱图像的处理系统需要具有数据吞吐率高、处理速度快及存储量大等特点,设计了一套以DSP和FPGA为核心处理器的嵌入式高光谱图像处理系统．系统采用USB接口10方式,选用TI公司TMS320C6000系列DSP和Altera公司的CycloneⅡ系列FPGA作为核心器件．首先给出了硬件实现总体框图,然后介绍了所采用的芯片,并详细叙述了FPGA周围电路的连接及系统工作原理,最后利用高光谱图像目标识别算法对系统加以验证．     

数字水准仪的数据采集与数据处理系统研究

介绍了数字水准仪数据采集系统的原理与设计。以及数据处理的方法。该数据采集系统硬件电路简单、设计成本低、使用方便。数据处理算法采用一维边缘检测算子的递归算子提取标尺条码边缘，大大降低了数据处理的运算量，提高了运算速度。实践证明了该方案的可行性。     

Rapid automated tracing and feature extraction from retinal fundus images using direct exploratory algorithms

Algorithms are presented for rapid, automatic, robust, adaptive, and accurate tracing of retinal vasculature and analysis of intersections and crossovers. This method improves upon prior work in several ways: automatic adaptation from frame to frame without manual initialization/adjustment, with few tunable parameters; robust operation on image sequences exhibiting natural variability, poor and varying imaging conditions, including over/under-exposure, low contrast, and artifacts such as glare; does not require the vasculature to be connected, so it can handle partial views; and operation is efficient enough for use on unspecialized hardware, and amenable to deadline-driven computing, being able to produce a rapidly and monotonically improving sequence of usable partial results. Increased computation can be traded for superior tracing performance. Its efficiency comes from direct processing on gray-level data without any preprocessing, and from processing only a minimally necessary fraction of pixels in an exploratory manner, avoiding low-level image-wide operations such as thresholding, edge detection, and morphological processing. These properties make the algorithm suited to real-time, on-line (live) processing and is being applied to computer-assisted laser retinal surgery.     

基于DSP和FPGA的红外信息数据处理系统

针对红外制导控制信息数据处理系统的功能分析,提出了采用DSP+FPGA的设计方案,即一种基于TMS320C6414与XC2V2000-FG676的信息数据处理系统设计方案,并从工作原理、硬件以及软件3个方面介绍了该系统的设计和实现方法。由DSP完成图像采集单元的信号采集及处理,由FPGA逻辑设计完成主机控制电路功能部分。本设计具有较高的通用性和可靠性,在红外成像导引系统中具有较高的实用价值和应用前景。     

A CMOS analog-digital audio processor for a portable radiotelephone

A mixed analog-digital (A/D) integrated circuit (IC) specifically designed to realize the audio processing functions needed for a portable radiotelephone (PRT) application is described. Multirate signal processing techniques are used to reduce the capacitance spread, and hence the overall silicon area, of the chip, as well as to minimize the settling requirements of the amplifiers for lower power consumption. This, together with programmable power-saving control circuitry also incorporated on-chip, considerably extends the lifetime of the battery. A semicustom design methodology is employed to implement such an application-specific integrated circuit (ASIC) in a 3-μm CMOS double-poly processing technology. Experimental results are presented to demonstrate the correct operation and functionality of the prototype chips     

基于比特平面的快速中值滤波器设计与实现

提出基于比特平面的快速中值滤波算法硬件实现结构和核心处理电路,在减少了中值滤波电路面积的情况下,显著提高了处理速度.提出的比特平面算法硬件实现结构的面积与滤波数据长度和量化比特教成近似线性关系,适于各种滤波窗口大小和数据精度的中值滤波;算法硬件实现结构规则,特别适于用FPGA实现.     

基于TMS320C6201图像采集和处理系统的硬件实现

影响图像采集和处理的主要因素之一是器件的处理速度问题,介绍了TMS320C6201的主要特点,提出了以TMS320C6201 DSP为核心处理器来研制高速图像采集和处理系统的硬件方案,给出了硬件实现总体框图,较详细叙述了图像处理模块和图像采集模块的主要功能和工作原理,从而为图像处理系统提供了新的高速实时处理硬件方案．