Evaluation of the nanoindentation behaviors of SiGe epitaxial layer on Si substrate

In this paper, ultra-high vacuum chemical vapor deposition (UHV/CVD) was employed to synthesize silicon-germanium (SiGe), and sequence to endure annealing treatment. Morphological characterization, roughness, and microstructural morphology were observed by means of scanning electron microscopy (SEM), atomic force microscopy (AFM), and transmission electron microscopy (TEM). The elements distribution, crystallographic, and nanomechanical behavior were carried out using energy-dispersive X-ray spectroscopy (EDS) mapping technique, X-ray diffraction (XRD), and nanoindentation technique.The annealing treated SiGe leads to the 2D germanium segregation on the surface. The phenomenon is interpreted in terms of dislocation-induced structural changes in annealing treatment. Thus, the dislocation propagation in the microstructure was observed. Subsequently hardness and elastic modulus were increased because of a comparatively unstable microstructure after annealing treatment.     

Investigation of the implanted phosphorus in a boron doped SiGe epitaxial layer

Phosphorus diffusion into strained SiGe layers was studied by different methods. Doping profiles and carrier concentration profiles N(x), depth of pn junction, Ge content in SiGe and thickness of epitaxial layer were measured and simulated. Several experimental methods such as secondary ion mass spectroscopy, spreading resistance method, Raman spectroscopy—and process simulator ISE TCAD have been used. The results obtained by different methods and at different places of work have been compared and analysed.     

(001)Si衬底上La0.9Sr0.1MnO3/SrTiO3外延生长薄膜的界面电子显微学研究

本文利用高分辨电子显微术、电子能量损失谱和电子全息技术对Si基体上生长的SrTiO3（STO）和La0.9Sr0.1MnO3（LSMO）薄膜及其STO层和Si基体之间的界面结构进行了深入研究,结果表明在Si和STO层之间由于氧扩散会形成一层过渡的SiOx无序层,且随沉积条件不同界面原子无序层厚度稍有不同;选区电子衍射结果表明薄膜和基体之间的外延生长关系为[001]LSMO//[^-110]Si,[110]LSMO//[001]Si[001]STO,//[001]Si,[010]STO//[110]Si;电子能量损失谱分析表明界面无序层中Si离子的氧化态处于Si^2＋和Si^0之间;电子全息结果清晰地显示了基体与薄膜之间存在明显的相位和势垒变化,负电荷聚集在界面SiOx的无序层中。     

Si衬底GaN基多量子阱外延材料的TEM研究

本文采用高分辨透射电子显微技术对在Si衬底生长的GaN基多量子阱外延材料的位错特征、外延层与衬底的晶体取向关系及界面的结晶形态等微观结构进行了分析和研究.结果表明:Si衬底生长的GaN与衬底有一定的取向关系;材料在MQW附近的穿透位错密度达108 cm-2量级,且多数为刃型位错;样品A的多量子阱下方可见平行于界面方向的...     

Fabrication and current-drive of SiGe/Si 'Micro-origami' epitaxial MEMS device on SOI substrate

A micromirror structure with SiGe/Si heteroepitaxial layer on a silicon-on-insulator (SOI) substrate using a 'Micro-origami' technique has been successfully fabricated. The micromirror is supported by two curved hinge structures. The device is driven by application of a current, and net angular displacements larger than 10/spl deg/ (static) and 30/spl deg/ (in resonance) were obtained. These values are comparable with or even larger than the reported values for other MEMS optical switches or beam scanning devices. The experimental results suggest that the movement is evoked by a thermal effect. The Micro-origami device has advantages of low operation voltage smaller than 2 V, and structural compatibility with the Si or SiGe LSIs.     

Influence of the oxygen content in SiGe on the parameters of Si/SiGe heterojunction bipolar transistors

We demonstrate peak f_T and f_max of 50 GHz for heterojunction bipolar transistors (HBTs) with an oxygen concentration in the epitaxial SiGe base layer of about 10²⁰ cm⁻³. These f_T/f_max values are over 10 GHz higher than for identically processed HBTs with an O content of only 10¹⁸ cm⁻³. This is due to reduced transient enhanced diffusion of boron in the O-rich layers. However, the base carrier lifetimes are reduced by the high oxygen content. We show that ideal base current characteristics and a low 1/fnoise level can be obtained despite this effect by localizing the emitter-base space-charge region outside the O-rich layer.     

RPCVD生长SiGe薄膜及其性能研究

利用应用材料公司外延设备,在Si(001)衬底上,通过RPCVD方式生长出完全应变、无位错的SiGe外延层.通过X射线衍射和原子力显微镜测试技术,得到了外延层Ge摩尔分数、外延层厚度、生长速率以及表面粗糙度等参数,研究了运用RPCVD方法制备的应变SiGe外延层的生长特性以及薄膜特性.结果表明,在660℃所生长的薄膜,其XRD图像均出现了Pendelossung条纹,表明薄膜质量较好.Ge摩尔分数高达16.5%.薄膜表面粗糙度RMS在0.3～0.6nm.     

SiGe/SiHBT异质界面与pn结界面的相对位移的影响

从模拟和实验两方面研究了SiGe/Si HBT发射结中pn结界面和SiGe/Si界面的相对位置对器件的电流增益和频率特性的影响.发现两界面偏离时器件性能会变差.尤其是当pn结位于SiGe/Si界面之前仅几十?就足以产生相当高的电子寄生势垒,严重恶化器件的性能.据此分析了基区B杂质的偏析和外扩对器件的影响以及SiGe/Si隔离层的作用.     

SiGe／Si HBT及其单片微波集成电路的研究

ＳｉＧｅ／Ｓｉ ＨＢＴ作为单片微波集成电路中的有源元件，在截止频率，增益，噪声等方面相对于ＧａＡｓ器件有很大的优势。本文结合本单位在ＳｉＧｅ材料和器件、电路等方面做过的工作，对实现ＳｉＧｅ单片微波集成电路的一些理论和技术要点作了阐述。     

功率SiGe/Si HBT的温度特性

测量了Si/SiGe HBT在23~260℃温度范围内的Gummel图、理想因子n、不同基极电流下的发射结电压VBE、电流增益β、共发射极输出特性,以及Early电压VA的变化情况。结果表明,随电流和温度的增加,β减少,VBE随温度的变化率dVBE/dT小于同质结Si BJT。在高集电极-发射极电压和大电流下,在输出特性曲线上观察到了负微分电阻(NDR)特性。结果还显示,电流增益-Early电压积与温度的倒数(1/T)呈线性关系,这对模拟电路应用是很重要和有用的。     

射频Si/SiGe/Si HBT的研究

在Si／SiGe／SiHBT与Si工艺兼容的研究基础上，对射频Si／SiGe／SiHBT的射频特性和制备工艺进行了研究，分析了与器件结构有关的关键参数寄生电容和寄生电阻与Si／SiGe/Si HBT的特征频率fT和最高振荡频率fmax的关系，成功地制备了fT为2．5CHz、fmax为2．3GHz的射频Si／SiGe／SiHBT，为具有更好的射频性能的Si／SiGe／Si HBT的研究建立了基础。     

Low-dislocation relaxed SiGe grown on an effective compliant substrate

An effective compliant substrate was successfully fabricated for growth of high quality relaxed SiGe templates. The compliant substrate was fabricated by synthesizing a 20% B₂O₃ concentration borosilicate glass in the silicon on insulator wafers through boron and oxygen implantation followed by high temperature annealing. Substrates with 5%, 10% and 20% B₂O₃ were used for 150 nm Si_0.75Ge_0.25 epitaxy. Double-axis x-ray diffraction measurements determined the relaxation and composition of the Si_1−xGe_x layers. Cross-sectional transmission electron microscopy was used to observe the lattice of the SiGe epilayer and the Si substrate, dislocation density and distribution. Raman spectros-copy was combined with step etching to measure the samples. For 20% BSG sample, the strain in the thin Si layer was calculated from the Raman shift and it matched the results from DAXRD very well. The density of threading dislocation on the surface of 500 nm Si_0.75Ge_0.25 layers was 2×10⁴ cm⁻² for the sample on the 20% borosilicate glass substrate. This method is promising to prepare effective compliant substrate for low-dislocation relaxed SiGe growth.     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟 ,给出了以提高跨导为目标的 Si/ Si Ge PMOSFET优化设计方法 ,包括栅材料的选择、沟道层中 Ge组分及其分布曲线的确定、栅氧化层及 Si盖帽层厚度的优化和阈值电压的调节 ,基于此已研制出 Si/ Si Ge PMOSFET器件样品 .测试结果表明 ,当沟道长度为 2μm时 ,Si/ Si Ge PMOS器件的跨导为 45 m S/ mm(30 0 K)和 92 m S/ mm (77K) ,而相同结构的全硅器件跨导则为 33m S/ mm (30 0 K)和 39m S/ m m (77K) .     

A comparison of thin film microrefrigerators based on Si/SiGe superlattice and bulk SiGe

Most of the conventional thermal management techniques can be used to cool the whole chip. Since thermal design requirements are mostly driven by the peak temperatures, reducing or eliminating hot spots could alleviate the design requirements for the whole package. Monolithic solid-state microcoolers offer an attractive way to eliminate hot spots. In this paper, we review theoretical and experimental cooling performance of silicon-based microrefrigerators on a chip. Both Si/SiGe superlattice and also bulk SiGe thin film devices have been fabricated and characterized. Direct measurement of the cooling along with material characterization allows us to extract the key factors limiting the performance of these microrefrigerators. Although Si/SiGe superlattice has larger thermoelectric power factor, the maximum cooling of thin film refrigerators based on SiGe alloys are comparable to that of superlattices. This is due to the fact that the superlattice thermal conductivity is larger than bulk SiGe alloy by about 30%.     

DESIGN AND FABRICATION OF Si/SiGe PMOSFETs

Based on theoretical analysis and computer-aided simulation, optimized design prin-ciples for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials, determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage.In the light of these principles, a SiGe PMOSFET is designed and fabricated successfully.Measurement indicates that the SiGe PMOSFET‘s(L=2μ同洒45 mS/mm(300K) and 92 mS/mm(77K) ,while that is 33mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.     

SiGe/Si HBT高频噪声特性研究

基于器件Y参数,对Si/Si1-xGexHBT的高频噪声进行了模拟。Si/Si1-xGexHBT的高频最小噪声系数随Ge组份x的增加而减小。与Si BJT相比,Si/SiGe HBT具有优异的高频噪声特性。     

Si间隔层对利用低温Si缓冲层生长高弛豫SiGe层的影响

利用低温生长Si缓冲层与Si间隔层相结合的方法生长高弛豫SiGe层,研究了Si间隔层在其中的作用. 利用化学腐蚀和光学显微镜，观察了不同外延层厚度处位错的腐蚀图样. 研究了不同温度下生长的Si间隔层对SiGe外延层中位错形成、传播及其对应变弛豫的影响. 结果表明Si间隔层的引入，显著改变了外延层中位错的形成和传播，进而使得样品表面形貌也呈现出较大的差异.     

Impact of the SiGe/Si interface structure upon the low temperature photoluminescence of a Si/Si1−xGex multiple quantum well

The effect of interfacial potential fluctuations of a Si/SiGe multiple quantum well structure upon the low-temperature exciton luminescence is reported. Exciton localisation at such potential fluctuations with a lateral period of 4–6 nm is observed as a strong blue-shift in the power dependence of the low-temperature photoluminescence (PL). To characterise the structure of the interfaces, X-ray diffraction and reflectivity, X-ray topography and transmission electron microscopy (TEM) were used. Moreover, annealing of the sample at temperatures well below the growth temperature leads to the formation of striations with a period of several micrometres along the [0 1 1] direction. These striations are due to Ge-concentration fluctuations and are accompanied by the observation of D-line emission due to misfit dislocations.     

Simulation and comparison of MOS inversion layer quantum mechanics effects in SiGe PMOSFET and Si PMOSFET

By employing the semiconductor device 2D simulator Medici, the inversion layer quantum mechanics effects (QME) in the strained SiGe-channel PMOSFET are studied. The influences of the inversion layer QME on the channel hole sheet density, the surface potential, the electric field and the threshold voltage in strained SiGe PMOS and Si PMOS are simulated and compared. It is theoretically predicted and validated by the numeric simulation results that QME lead to much difference in device performance between SiGe PMOS and Si PMOS. This study shows that SiGe PMOS suffers less disadvantageous influence when compared with Si PMOS, in ultra-deep submicron dimension, where QME are becoming increasingly more important.     

A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure, a 0.8-μm Si_0.1 Ge_0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si_0.1Ge_0.9 layer. A 0.8-μm Si_0.05Ge_0.95 layer and a 1-μm top Ge layer were subsequently grown. The strained Si_0.05Ge_0.95/Si_0.1Ge_0.9 and Ge/Si_0.05Ge_0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1–3-μm GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600°C. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 μm (2.6-μm SiGe-buffer structure +2.5-μm GaAs layer).