Evaluation of the bonded silicon on insulator (SOI) wafer and thecharacteristics of PIN photodiodes on the bonded SOI wafer

Electrical properties of the bonded silicon on insulator (SOI) wafer and characteristics of PIN photodiodes fabricated on the SOI layer were evaluated. A trap with deep energy level (about Ec-Et=0.55 eV) was observed in the SOI layer with 100 μm- and 30 μm-thickness using the deep level transient spectroscopy (DLTS) method. No trap was detected in the SOI layer with 10 μm-thickness. This deep trap was not observed before the wafer bonding process and thus the trap is generated during the wafer bonding process. From primary mode lifetime (τ₁) measurements, it is considered that the trap will works as the generation center or the recombination center. For PIN photodiodes on the SOI layer in which the trap was detected, the increases of dark current were observed. Spectral responses of photodiodes on the SOI layer were almost the same as that on the normal FZ-Si wafer. We fabricated PIN photodiodes with good spectral response     

Development of a fabrication process for parallel multijunction thin film silicon solar cells on wafer substrates

The parallel multijunction (PMJ) cell design theoretically enables high efficiency thin film polysilicon solar cells at lower cost. Since its initial proposal in 1994 the PMJ cell has been the subject of a number of theoretical studies, however, no detailed experimental investigation has yet been reported. Any systematic study of the PMJ solar cell will require suitably designed and fabricated devices to serve as experimental test‐beds. This paper reports the successful development of a fabrication sequence for PMJ cells in CVD‐epilayers on inert single‐crystal silicon substrates, producing cells with efficiencies up to 13%. The processing sequence is based on photolithography, anisotropic wet etching, high temperature furnace steps and evaporated metallisation. Full details of the processing sequence are provided, with explanations of particular process choices, including the method of parallel electrical connection of like‐polarity layers, the use of a thick photoresist (Shipley SJR5740), avoiding pitfalls, and procedures to minimise cell shunt behaviour. The establishment of this baseline fabrication sequence for PMJ cells opens up a wealth of opportunities for systematic studies of cell performance limiting mechanisms, such as junction recombination, and the implications of various cell design and processing options, particularly those likely to be of more commercial relevance, such as laser scribing, laser doping, rapid thermal processing and electroless metal plating. Copyright © 2000 John Wiley & Sons, Ltd.     

Solid phase crystallization of amorphous silicon on glass by thin film heater for thin film transistor (TFT) application

A new process for solid phase crystallization (SPC) of amorphous silicon (a-Si) using thin film heater is reported. With this localized Ti silicide thin film heater, we successfully crystallized 500 Å-thick a-Si in a few minutes without any thermal deformation of glass substrate. The size of crystallized silicon grain was abnormally big (30-40 μm). Polycrystalline thin film transistors (TFT) fabricated using this unique thin film heater showed better mobility than those of conventional ones by furnace annealing.     

Very thin film crystalline silicon solar cells on glass substratefabricated at low temperature

The performances of thin-film poly-Si solar cells with a thickness of less than 5 μm on a glass substrate have been investigated. The cell of glass/back reflector/n-i-p-type Si/ITO is well characterized by the structure of naturally surface texture and enhanced absorption with a back reflector (STAR), where the active i-type poly-Si laser was fabricated by plasma chemical vapor deposition (CVD) at low temperature. The cell with a thickness of 2.0 μm demonstrated an intrinsic efficiency of 10.7% (aperture 10.1%), the open-circuit voltage of 0.539 V and the short current density of 25.8 mA/cm² as independently confirmed by Japan Quality Assurance, which shows the no clear light-induced degradation. The optical and transport properties of poly Si cells are summarized     

Comparison of thin epitaxial film silicon photovoltaics fabricated on monocrystalline and polycrystalline seed layers on glass

We fabricate thin epitaxial crystal silicon solar cells on display glass and fused silica substrates overcoated with a silicon seed layer. To confirm the quality of hot‐wire chemical vapor deposition epitaxy, we grow a 2‐µm‐thick absorber on a (100) monocrystalline Si layer transfer seed on display glass and achieve 6.5% efficiency with an open circuit voltage (V_OC) of 586 mV without light‐trapping features. This device enables the evaluation of seed layers on display glass. Using polycrystalline seeds formed from amorphous silicon by laser‐induced mixed phase solidification (MPS) and electron beam crystallization, we demonstrate 2.9%, 476 mV (MPS) and 4.1%, 551 mV (electron beam crystallization) solar cells. Grain boundaries likely limit the solar cell grown on the MPS seed layer, and we establish an upper bound for the grain boundary recombination velocity (S_GB) of 1.6x10⁴ cm/s. Copyright © 2014 John Wiley & Sons, Ltd.     

Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic

This paper presents design considerations along with measurement results pertinent to hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) drive circuits for active matrix organic light emitting diode (AMOLED) displays. We describe both pixel architectures and TFT circuit topologies that are amenable for vertically integrated, high aperture ratio pixels. Here, the OLED layer is integrated directly above the TFT circuit layer, to provide an active pixel area that is at least 90% of the total pixel area with an aperture ratio that remains virtually independent of scaling. Both voltage-programmed and current-programmed drive circuits are considered. The latter provides compensation for shifts in device characteristics due to metastable shifts in the threshold voltage of the TFT. Various drive circuits on glass and plastic were fabricated and tested. Integration of on-panel gate drivers is also discussed where we present the architecture of an a-Si:H based gate de-multiplexer that is threshold voltage shift invariant. In addition, a programmable current mirror with good linearity and stability is presented. Programmable current sources are an essential requirement in the design of source driver output stages.     

A novel way of texturing glass for microcrystalline silicon thin film solar cells application

In this paper, we present a novel way of texturing glass facilitated by ZnO:Al thin film as sacrificial layer for thin film silicon solar cell application. We name this technique zinc oxide‐induced texturing (ZIT). The texturing of glass was achieved by wet etching of ZnO:Al covered glass with HF and HNO₃ as etchants. We investigated the influence of the ZnO:Al layer sputtering condition, the layer thickness, and the etchant composition on the surface morphology of the textured glass. We demonstrate that we are able to control the roughness of the ZIT glass over a wide roughness range, ranging from 20 to 400 nm. Highly efficient microcrystalline silicon n‐i‐p solar cells were deposited on ZIT glass. The influence of the substrate morphology on the solar cell performance is also discussed. The highest efficiency for a single junction n‐i‐p microcrystalline silicon solar cell obtained in this work is 10.64% (Active area). Copyright © 2014 John Wiley & Sons, Ltd.     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

柔性衬底硅薄膜太阳电池中ZGO薄膜的应用

在室温下,采用孪生对靶直流磁控溅射工艺,在玻璃衬底上制备出高质量的Ga掺杂ZnO(ZnO:Ga)透明导电膜。研究了薄膜厚度对薄膜的结构、光学及电学特性的影响。制备的ZnO:Ga是具有六角纤锌矿结构的多晶薄膜,最佳择优取向为(002)方向。随着薄膜厚度的增加,衍射峰明显增强,晶粒增大。优化反应条件,薄膜的电阻率达到4.69×10-4Ω.cm,在可见光范围内平均透过率达到了85%以上。将不同厚度的ZnO:Ga薄膜(350～820 nm)在柔性聚酰亚胺衬底nip非晶硅(a-Si)薄膜太阳电池中,随厚度的增加,电池的填充因子和效率都得到了提高,得到聚酰亚胺衬底效率7.09%的a-Si薄膜太阳电池。     

硅薄膜太阳电池的电致发光与Ⅰ-Ⅴ特性研究

研究了薄膜太阳电池电致发光特性,并运用AAA极太阳模拟器测试其I-V特性。采用高灵敏度光谱仪检测薄膜电池电致发光的光谱波长在860 nm之间,讨论其对 应禁带宽度为1.12 eV;运用制冷的CCD相机探测电致发光的EL 图像,分析不同的薄膜电池在相同偏 压80V下电致发光强度与其电性能的内在关系;研究不同偏压35 V\ 55 V\80 V下,电压、电流与薄膜电池的 EL发光强度正相关性;结果分析表明串联电阻太高对电压具有分压作用导致发光光谱强度 减弱,并联电阻 太低具有分流作用电致发光强度减弱,通过电致发光检测和电性能测试相结合可为硅薄膜电 池的工艺改进提供快速、准确的判断依据。     

氮化硅薄膜MIM电容器的制备与性能研究

在被釉氧化铝陶瓷基片上,采用真空电阻蒸发法和等离子体增强化学气相沉积法制备了Au/NiCr电极薄膜及氮化硅(SiNx)介质薄膜,并对薄膜进行光刻图形化,制成了Au/NiCr/SiNx/Au/NiCr结构的MIM电容器。研究了所制电容器的介电性能、介温性能和I-V特性等电学性能。结果表明:所得MIM电容器具有很低的介电损耗(1MHz时tanδ为0.00192)及很高的电压稳定性;在–55～+150℃的范围内其1MHz时的电容温度系数为258×10–6/℃;另外,其I-V特性曲线显示出较好的对称性,漏电流密度较低,可承受较高的电压。     

非晶硅薄膜太阳能电池应用开发新进展

非晶硅（ａ－Ｓｉ）薄膜太阳能电池是取之不尽的洁净能源－太阳能的光电元（组）件。文章详述了ａ－Ｓｉ薄膜太阳能电池的工艺优势，市场开发状况，可能应用领域，存在问题和展望。     

Characterization of thin textured tunnel oxide prepared by thermaloxidation of thin polysilicon film on silicon

In this paper, the characteristics of thin textured tunnel oxide prepared by thermal oxidation of thin polysilicon film on Si substrate (TOPS) are studied. Because of the rapid diffusion of oxygen through the grain boundaries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at the grain boundaries, the oxidation rate of the TOPS sample is close to that of a normal oxide grown on a (111) Si substrate. Also, a textured Si/SiO₂ interface is obtained. The textured Si/SiO₂ interface results in localized high fields and causes a much higher electron injection rate. The optimum TOPS sample can be obtained by properly oxidizing the stacked α-Si film, independent of the substrate doping level. Also, the optimum TOPS sample exhibits a smaller electron trapping rate and a lower interface state generation rate when compared to the sample from a standard tunnel oxide process. These differences are attributed to a lower bulk electric field and a smaller injection area in the TOPS samples     

Impact of light soaking and thermal annealing on amorphous silicon thin film performance

Nowadays, there is a wide debate in literature related to the silicon thin films seasonal performance. Amorphous modules seem to react positively to the temperature, while the temperature parameters indicate a negative thermal response. Periodic fluctuations of nominal power due to light soaking and thermal annealing effects are observed. On the other hand, the module temperature reached in some open rack plants seems too low to activate annealing power regeneration process so that the seasonal performance trend may depend mainly on other effects such as spectral or irradiance. In the following paper, a model that allows to calculate the impact of all the phenomena that affect the photovoltaic performance is used. The light soaking and thermal annealing contributions are measured from outdoor data using two different methods. Both methods lead to similar results, and the model is able to reproduce the seasonal performance with an acceptable level of reliability on the day, hour, minute time scale. An analysis of each effect contribution to the seasonal performance is also provided. Thus, main open questions related to a‐Si thin films performance such as positive reaction to temperature and seasonal fluctuations are discussed. Copyright © 2015 John Wiley & Sons, Ltd.     

Visualized characterization of slurry film between wafer and padduring chemical mechanical planarization

Chemical mechanical planarization (CMP) has emerged recently as an indispensable processing technique for planarization in submicrometer multilevel very large scale integration (VLSI). The demand from industry for fast material removal and a high degree of uniformity has been a serious challenge for the advancement of this key technology. Among various process aspects, the slurry flow between wafer and pad plays an important role in the pursuit of these goals. This study provides a visualized characterization of the amount and distribution of the fluid film between the wafer and pad. The fluid film is analyzed by the digital picture obtained through the transparent carrier and dyed fluid. The effects of process parameters are extensively investigated, including platen and carrier speed, pad design, rinsing location, and flow rate of slurry and wafer size. Suggestions for process recipes aiming at fast and uniform CMP are drawn based on the current results     

ZnS thin film deposition on Silicon and glass substrates by Thermionic vacuum Arc

In this study, Silicon (Si) and glass substrates were coated with Zinc sulfide (ZnS) using Thermionic Vacuum Arc (TVA) technique for the first time. With this technique, the coating time of the samples is very short and film thickness can be controlled during the coating process. Moreover, TVA provides many advantages to deposited thin films than other techniques such as compactness, low roughness, nanostructures, homogeneities as compared to other deposition techniques. This paper presents a different technique for deposition of high-quality ZnS thin films. Scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDX) and atomic force microscopy (AFM) were used to characterize the coated silicon and glass surface morphologies. Additionally, transmittances, thickness and refractive indices of coated glass samples with ZnS were measured by ultraviolet–visible spectrophotometer and interferometer to characterize their optical properties.     

Characterization of the microstructure of Co thin film on silicon substrate by TEM

The microstructure of as-deposited Co thin films on silicon (001) substrate was characterized by TEM using wedge-shaped planar-view samples. Selected area electron diffraction showed that the as deposited Co thin films were composed of Co (α) and that no interfacial reaction took place between Co thin films and the Si substrate. The microstructure of Co thin films annealed at 250°C for 30 min was also investigated by using conventional planar-view samples. The analysis of selected area electron diffraction indicates that Co thin films react entirely with the Si substrate, and a silicide layer forms at the Co/Si interface. Dark field images clearly indicate that the interfacial layer consists of Co₂Si in irregular stripes and CoSi as fine particles but no CoSi₂ forms.     

Lambertian matched absorption enhancement in PECVD poly‐Si thin film on aluminum induced textured glass superstrates for solar cell applications

This paper examines the effectiveness of a range of aluminum induced textured (AIT) glass topographies at enhancing light absorption in silicon thin film diode structures deposited on the textured glass side, operating in the superstrate configuration. The aluminum layer used to produce the AIT can be deposited either by thermal evaporation or magnetron sputtering. Varying AIT process parameters produces a wide range of feature roughness and uniformity, providing scope to optimize texture effectiveness and process repeatability. We report strong correlation between the degree of absorption enhancement from these textures and both dark field microscope images of the AIT glass and reduction of the interference envelope in spectral reflectance of the deposited silicon films. Our findings corroborate earlier modeling work based on ray tracing, which predicted that the best enhancement occurs when the feature size is close to the film thickness. In this paper we investigate AIT samples in the 1 – 3 µm film thickness range, some of which trap light in silicon as strongly as at the Lambertian limit. Copyright © 2010 John Wiley & Sons, Ltd.     

表面阳极氧化铝结构对ZnO薄膜探测器的响应增强

通过在ZnO外延薄膜上淀积一层Al薄膜,并利用Al膜叉指型光刻胶图案为掩模,可以选择性地将叉指间无光刻胶区域下的Al膜阳极氧化,在ZnO表面形成氧化铝微纳结构,而在光刻胶掩模下未被阳极氧化的Al膜便成为ZnO紫外光电导探测器的叉指电极.用此法制备的非周期性氧化铝结构具有相近的孔大小和间距,形成可以在平面内全方位大角度衍射的光栅矢量.入射光可以被ZnO有阳极氧化铝结构的探测器比无此结构的器件在同等条件下的光响应度提高到了1.8倍.