Residual stress in silicon nitride films

The mechanical stress caused by Si₃N₄ films on (111) oriented Si wafers was studied as a function of the Si₃N₄ film thickness, deposition rate, deposition temperature and film composition. The Si₃N₄ films were prepared by the reaction of gaseous SiH₄ and NH₃ in the temperature range 700–1000°C. The curvature of the Si substrates caused by the Si₃N₄. films is related to the film stress; the substrate curvature was measured by an optical interference technique. The measured Si₃N₄. film stress was found to be highly tensile with a magnitude of about 10¹⁰ dynes/cm². For the thickness range of 2000–5000Å, there was no change in the measured stress. The total film stress was observed to decrease for decreasing deposition rate and increasing deposition temperature. A large change in film stress was observed for films containing excess Si; the stress decreased with increasing Si content. Based on published values for the thermal expansion coefficients for Si and Si₃N₄, a published value for Young’s Modulus for Si₃N₄, and the measured total stress values, a consistent argument is developed in which the total stress consists of a compressive component due to thermal expansion coefficient mismatch and a larger tensile intrinsic stress component. Both the thermal and intrinsic stress components vary with film deposition temperature in directions which decrease the total room temperature stress for higher deposition temperatures.     

An Integrated Experimental and Computational System for the Thermal Characterization of Complex Three-Dimensional Submicron Electronic Devices

This work presents the creation of a coupled analysis engine and experimental system capable of fully characterizing the thermal behavior of complex, 3D, active, submicron, electronic devices. First, the surface temperature field of an activated device is non-invasively measured with submicron spatial resolution. Next, the thermal conductivity of each thin-film layer composing the device is measured and a numerical model is built using these values. The measured temperature distribution map is then used as input for an ultra-fast inverse computational solution to fully characterize the thermal behavior of the complex 3D device. By bringing together measurement and computation, it becomes possible for the first time to non-invasively extract the 3D thermal behavior of nanoscale embedded features that cannot otherwise be accessed. The power of the method was demonstrated by verifying that it can extract details of interest of a representative MOSFET device.     

The influence of defects on device performance of MBE-grown Si homojunction and strained Si1-xGex/Si heterostructures

Different Si homojunction and strained Si_1-xGe_x/Si heterojunction diodes and bipolar transistors have been fabricated by Si-MBE. The effect of annealing on Si homojunction diodes and transistors are studied. It is found that annealing generally improves the Si device performance, such as the ideality factor and breakdown characteristics. The influence of⁶⁰Co γ irradiation on the Si_1-xGe_x/Si diode performances are investigated by studying the temperature dependence of their electrical characteristics, and the results are correlated with the quality of the MBE-films. γ irradiation causes a drop in material conductivity due to the generation of atom-displacement defects in the whole volume of the wafers and increases the defect density at hetero-interfaces. The forward I-V curves of Si_1-xGe_x/Si devices may shift towards lower or higher voltages, depending on the film quality and the irradiation dose. The increase of defect density in strained Si_1-xGe_x/Si films appears to occur easier for the films with lower quality. Electrical measurements and calculations show that the defect-associated tunneling process is important in current transport for these MBE grown Si homojunction and strained Si_1-xGe_x/Si heterojunction devices, which have initially medium film quality or have been treated by irradiation.     

Modeling of Thermoelectric Properties of Magnesium Silicide (Mg2Si)

Thermoelectric (TE) materials based on alloys of magnesium (Mg) and silicon (Si) possess favorable properties such as high electrical conductivity and low thermal conductivity. Additionally, their abundance in nature and lack of toxicity make them even more attractive. To better understand the electronic transport and thermal characteristics of bulk magnesium silicide (Mg₂Si), we solve the multiband Boltzmann transport equation within the relaxation-time approximation to calculate the TE properties of n-type and p-type Mg₂Si. The dominant scattering mechanisms due to acoustic phonons and ionized impurities were accounted for in the calculations. The Debye model was used to calculate the lattice thermal conductivity. A unique set of semiempirical material parameters was obtained for both n-type and p-type materials through simulation testing. The model was optimized to fit different sets of experimental data from recently reported literature. The model shows consistent agreement with experimental characteristics for both n-type and p-type Mg₂Si versus temperature and doping concentration. A systematic study of the effect of dopant concentration on the electrical and thermal conductivity of Mg₂Si was also performed. The model predicts a maximum dimensionless figure of merit of about 0.8 when the doping concentration is increased to approximately 10²⁰?cm^?C3 for both n-type and p-type devices.     

Enhanced infrared transmission of GZO film by rapid thermal annealing for Si thin film solar cells

Ga doped ZnO (GZO) films prepared by sputtering at room temperature were rapid thermal annealed (RTA) at elevated temperatures. With increasing annealing temperature up to 570°C, film transmission enhanced significantly over wide spectral range especially in infrared region. Hall effect measurements revealed that carrier density decreased from ∼8 × 10²⁰ to ∼ 3 × 10²⁰ cm⁻³ while carrier mobility increased from ∼15 to ∼28 cm²/Vs after the annealing, and consequently low film resistivity was preserved. Hydrogenated microcrystalline Si (µc‐Si:H) and microcrystalline Si_1‐xGe_x (µc‐Si_1‐xGe_x:H, x = 0.1) thin film solar cells fabricated on textured RTA‐treated GZO substrates demonstrated strong enhancement in short‐circuit current density due to improved spectral response, exhibiting quite high conversion efficiencies of 9.5% and 8.2% for µc‐Si:H and µc‐Si_0.9Ge_0.1:H solar cells, respectively. Copyright © 2011 John Wiley & Sons, Ltd.     

Quantifying self-heating effects with scaling in globally strained Si MOSFETs

Electrical results are presented for deep submicron strained Si MOSFETs fabricated on both thick and thin SiGe strain relaxed buffers, SRBs. For the first time thin SRB devices are shown to offer the same performance enhancements as thick SRB devices. The reduction in performance enhancement with device scaling widely reported in the literature has also been investigated. Correcting for dynamic self-heating effects using ac measurements, the enhancements seen in long channel devices are maintained down to short channel lengths, demonstrating the scalability of SRB technology. Thermal resistances have been measured experimentally and compared with analytical models. The thermal resistance for devices on the thin SRBs is reduced by 50% compared with devices on thick SRBs. Finally, a comparison of self-heating effects in MOSFETs fabricated on SOI and Si_0.8Ge_0.2 SRBs provides insight into the challenges ahead as power densities continue to increase.     

Power transistors fabricated using isotopically purified silicon (/sup 28/Si)

It is well known that isotopic purification of group IV elements can lead to substantial increases in thermal conductivity due to reduced scattering of the phonons. The magnitude of the increase in thermal conductivity depends on the level of isotopic purification, the chemical purity, as well as the test temperature. For isotopically pure silicon (/sup 28/Si) thermal conductivity improvements as high as sixfold at 20 K and 10%-60% at room temperature have been reported. Device heating during operation results in degradation of performance and reliability (electromigration, gate oxide wearout, thermal runaway). In this letter, we discuss the thermal performance of packaged RF LDMOS power transistors fabricated using /sup 28/Si. A novel technique allows the cost effective deployment of this material in integrated circuit manufacturing. A clear reduction of about 5/spl deg/C-7/spl deg/C in transistor average temperature and a corresponding 5%-10% decrease in overall packaged device thermal resistance is consistently measured by infrared microscopy in devices fabricated using /sup 28/Si over natural silicon.     

Nanostructured Bulk Silicon as an Effective Thermoelectric Material

Thermoelectric power sources have consistently demonstrated their extraordinary reliability and longevity for deep space missions and small unattended terrestrial systems. However, more efficient bulk materials and practical devices are required to improve existing technology and expand into large‐scale waste heat recovery applications. Research has long focused on complex compounds that best combine the electrical properties of degenerate semiconductors with the low thermal conductivity of glassy materials. Recently it has been found that nanostructuring is an effective method to decouple electrical and thermal transport parameters. Dramatic reductions in the lattice thermal conductivity are achieved by nanostructuring bulk silicon with limited degradation in its electron mobility, leading to an unprecedented increase by a factor of 3.5 in its performance over that of the parent single‐crystal material. This makes nanostructured bulk (nano‐bulk) Si an effective high temperature thermoelectric material that performs at about 70% the level of state‐of‐the‐art Si_0.8Ge_0.2 but without the need for expensive and rare Ge.     

Electronic properties of Si/Si-Ge Alloy/Si(100) heterostructures formed by ECR Ar plasma CVD without substrate heating

By using our low-energy Ar plasma enhanced chemical vapor deposition (CVD) at a substrate temperature below 100 °C during plasma exposure without substrate heating, modulation of valence band structures and infrared photoluminescence can be observed by change of strain in a Si/strained Si_0.4Ge_0.6/Si(100) heterostructure. For the strained Si_0.5Ge_0.5 film, Hall mobility at room temperature was confirmed to be as high as 660 cm² V⁻¹ s⁻¹ with a carrier concentration of 1.3×10¹⁸ cm⁻³ for n-type carrier, although the carrier origin was unclear. Moreover, good rectifying characteristics were obtained for a p⁺Si/nSi_0.5Ge_0.5 heterojunction diode. This indicates that the strained Si-Ge alloy and Si films and their heterostructures epitaxially grown by our low-energy Ar plasma enhanced CVD without substrate heating can be applicable effectively for various semiconductor devices utilizing high carrier mobility, built-in potential by doping and band engineering.     

Self-Assembled Germanium Quantum-Dot Supercrystals in Silicon with Extremely Low Thermal Conductivities for Thermoelectrics

Superlattices with one-dimensional (1D) phonon confinement were studied to obtain a low thermal conductivity for thermoelectrics. Since they are composed of materials with a lattice mismatch, they often show dislocations. Like 1D nanowires, they also decrease heat transport in only one main propagation direction. It is therefore challenging to design superlattices with a thermoelectric figure of merit ZT higher than unity. Epitaxial self-assembly is a major technology to fabricate three-dimensional (3D) Ge quantum-dot (QD) arrays in Si. They have been used for quantum and solar-energy devices. Using the atomic-scale phononic crystal model, 3D Ge QD supercrystals in Si also present an extreme reduction of the thermal conductivity to a value that can be under 0.04 W/m/K. Owing to incoherent phonon scattering, the same conclusion holds for 3D supercrystals with moderate QD disordering. As a result, they might be considered for the design of highly efficient complementary metal–oxide–semiconductor (CMOS)-compatible thermoelectric devices with ZT possibly much higher than unity. Such a small thermal conductivity was only obtained for two-dimensional layered WSe₂ crystals in an experimental study. However, electronic conduction in the Si/Ge compounds is significantly enhanced. The 0.04 W/m/K value can be computed for different Ge QD filling ratios of the Si/Ge supercrystal with size parameters in the range of current fabrication technologies.     

Role of a Si0.95Ge0.05 epilayer cap on boron diffusion in silicon under inert and dry oxidizing ambient annealing

Silicon (Si) and Si with a 60 nm Si_0.95Ge_0.05 epilayer cap (Si_0.95Ge_0.05/Si) were implanted with 60 keV, 1×10¹³ cm⁻² boron (B) followed by annealing in nitrogen (N₂) or dry oxygen (O₂) in two different anneal conditions. B⁺implantation energy and dose were set such that the B peak is placed inside Si in Si_0.95Ge_0.05/Si samples and concentration independent B diffusion is achieved upon annealing. For samples annealed above 1075 °C, Ge diffusing from the Si_0.95Ge_0.05 epilayer cap in Si_0.95Ge_0.05/Si samples reached the B layer inside Si and resulted in retarded B diffusion compared to the Si samples. For annealing done at lower temperatures, diffusion of Ge from Si_0.95Ge_0.05 epilayer cap does not reach the B layer inside Si. Thus B diffusion profiles in the Si and Si_0.95Ge_0.05/Si samples appear to be similar. B diffusion in dry oxidizing ambient annealing of Si_0.95Ge_0.05/Si samples further depends on the nature of Si_0.95Ge_0.05 oxidation which is set by the duration and the thermal budget of the oxidizing anneal.     

Thermoelectric Properties of Hot-Pressed Materials Based on Mg2Si n Sn1−n

Mg₂Si _n Sn_1?n solid solutions consist of nontoxic widespread elements. In this work a number of samples of Mg₂Si _n Sn_1?n solid solutions, where 1 ≥ n ≥ 0.7 with various carrier concentrations, were obtained using microcrystalline powder by hot pressing in vacuum. The Seebeck coefficient and the thermal and electrical conductivity were measured in the temperature range from 300 K to 800 K. It is shown that the specific thermoelectric figure of merit (the ratio of the thermoelectric figure of merit to the material density) of these samples weakly depends on the composition of the solid solution. Hence, whether a solid solution or pure Mg₂Si is used depends on the application temperature of the material.     

Thermally Conductive Reduced Graphene Oxide Thin Films for Extreme Temperature Sensors

Reduced graphene oxide (RGO) films are promising in applications ranging from electronics to flexible sensors. Though high electrical and thermal conductivities have been reported for RGO films, existing thermal conductivity data for RGO films show large variations from 30 to 2600 W m^?1 K^?1. Further, there is a lack of data at low temperatures (<300 K), which is critical for the understanding of thermal transport mechanisms. In this work, a temperature‐dependent study of thermal (10–300 K) and electrical (10–3000 K) transport in annealed RGO films indicates the potential application of RGO films for sensing temperatures across an extremely wide range. The room‐temperature thermal conductivity increases significantly from 46.1 to 118.7 W m^?1 K^?1 with increasing annealing temperature from 1000 to 3000 K with a corresponding increase in the electrical conductivity from 5.2 to 1481.0 S cm^?1. In addition, films reduced at 3000 K are promising for sensing extreme temperatures as demonstrated through the measured electrical resistivity from 10 to 3000 K. Sensors based on RGO films are advantageous over conventional temperature sensors due to the wide temperature range and flexibility. Thus, this material is useful in many applications including flexible electronics and thermal management systems.     

Investigation of Si/SiGe/Si heterostructure implanted by H ion and annealed in vacuum and dry O2 ambient

The 20-nm-thick Si cap layer/74-nm-thick Si_0.72Ge_0.28 epilayer/Si heterostructures implanted by 25 keV H⁺ ion to a dose of 1×10¹⁶ cm⁻² were annealed in ultra-high vacuum ambient and dry O₂ ambient at the temperature of 800 °C for 30 min, respectively. Rutherford backscattering/ion channeling (RBS/C), Raman spectra, high-resolution X-ray diffraction (HRXRD) and atomic force microscopy (AFM) were used to characterize the structural characteristics of the Si_0.72Ge_0.28 layer. Investigations by RBS/C demonstrated that the crystal quality of the Si/Si_0.72Ge_0.28/Si heterostructure sample implanted by 25 keV H⁺ in conjunction with subsequent annealing in dry O₂ ambient is superior to that of identical sample annealing in ultra-high vacuum ambient. The less strain relaxation of SiGe layer of the Si/Si_0.72Ge_0.28/Si heterostructures implanted by H ion and annealed in dry O₂ ambient at the temperature of 800 °C for 30 min could be doublechecked by Raman spectra as well as HRXRD, which was compared with that in an identical sample annealed in ultra-high vacuum ambient for identical thermal budget. In addition, the SiGe layer of the H-implanted Si/SiGe/Si heterostructural sample annealed in dry O₂ ambient accompanied by better crystal quality and less strain relaxation made its surface morphology superior to that of the sample annealed in ultra-high vacuum ambient at the temperature of 800 °C for 30 min, which was also verified by AFM images.     

Analysis of “on” and “off” times for thermally driven VO2 metal-insulator transition nanoscale switching devices

Vanadium oxide undergoes a sharp metal-insulator transition in the vicinity of room temperature and there is considerable interest in exploring novel device applications that utilize this phase transition. Using experimentally determined values of the thermal conductivity across the metal-insulator transition in VO₂ thin films, we estimate the switching characteristics of two-terminal VO₂ devices. The minimum switching time for both heating (“on” state) and cooling (“off” state) processes is explored using a simple resistance-capacitance thermal circuit model. The estimated minimum switching time is on the order of ∼1 ns for 20 nm VO₂ films which is comparable to experimentally observed switching times. Optimal operating temperatures to maximize switching times are estimated. Methods to further enhance the switching kinetics by device thickness, carrier doping/strain, interfacial thermal resistance and input thermal energy are discussed. The simulations are compared with a 3-D model for VO₂ devices on Si substrates utilizing COMSOL. The results are of potential relevance to the emerging field of correlated oxide electronics with fast phase transitions.     

Submicron Mapping of Thermal Conductivity of Thermoelectric Thin Films

A tool for evaluating thin-film thermal conductivity to submicron spatial resolution has been developed. The micro-instrumentation utilizes the thermoreflectance (TR) technique to characterize thermal conductivity and material uniformity. The instrument consists of a heating element for creating temperature gradients and an Invar bar with in?situ temperature monitoring for heat flux measurements. The thin-film sample is sandwiched between the heater and Invar bar while a microscope is used to direct light onto a cross-section of the sample and reflected light is collected with a camera. By using this technique, we can achieve submicron spatial resolution for thermal conductivity and eliminate contributions from thermal contact resistance, thereby also eliminating the need for sample preparation other than cleaving. The method offers temperature resolution of 10?mK, spatial resolution of 200?nm, and thermal conductivity measurement with 0.01?±?0.001?W/mK resolution. The thermal conductivity of a 0.6% ErAs:InGaAlAs thermoelectric (TE) element, prepared by molecular beam epitaxy (MBE) growth, obtained with the new instrument is 2.3?W/mK, while the average thermal conductivity obtained with the 3-omega method is 2.5?W/mK. Energy-dispersive x-ray (EDX) spectroscopy is also used to prove that the elemental composition has uniformity consistent with the material variation observed by the TR technique. Moreover, a temperature profile across a 0.6% ErAs:InGaAlAs TE element on InP substrate is imaged. Two different slopes, corresponding to different thermal conductivities, have been observed, showing that the thermal conductivity of the TE element is lower than that of the InP substrate as expected.     

Transport and Mechanical Properties of High-ZT Mg2.08Si0.4−x Sn0.6Sb x Thermoelectric Materials

Mg₂(Si,Sn) compounds are promising candidate low-cost, lightweight, nontoxic thermoelectric materials made from abundant elements and are suited for power generation applications in the intermediate temperature range of 600 K to 800 K. Knowledge on the transport and mechanical properties of Mg₂(Si,Sn) compounds is essential to the design of Mg₂(Si,Sn)-based thermoelectric devices. In this work, such materials were synthesized using the molten-salt sealing method and were powder processed, followed by pulsed electric sintering densification. A set of Mg_2.08Si_0.4?x Sn_0.6Sb _x (0 ≤ x ≤ 0.072) compounds were investigated, and a peak ZT of 1.50 was obtained at 716 K in Mg_2.08Si_0.364Sn_0.6Sb_0.036. The high ZT is attributed to a high electrical conductivity in these samples, possibly caused by a magnesium deficiency in the final product. The mechanical response of the material to stresses is a function of the elastic moduli. The temperature-dependent Young’s modulus, shear modulus, bulk modulus, Poisson’s ratio, acoustic wave speeds, and acoustic Debye temperature of the undoped Mg₂(Si,Sn) compounds were measured using resonant ultrasound spectroscopy from 295 K to 603 K. In addition, the hardness and fracture toughness were measured at room temperature.     

The effect of low pressure chemical vapor deposition of silicon nitride on the electronic interface properties of oxidized silicon wafers

The effect of LPCVD Si₃N₄ film deposition on oxidized Si wafers, to form Si₃N₄/SiO₂/Si stacks, is studied using capacitance–voltage and carrier lifetime measurements. The deposition of a nitride film leads to an increase in the density of defects at the Si–SiO₂ interface, with the increase being greater the thinner the oxide. However, even the presence of a very thin intermediate oxide results in a dramatic improvement in interface properties compared to the direct deposition of the Si₃N₄ film on Si. The interface degradation occurs in the initial stages of nitride film deposition and appears to be largely the result of increased interfacial stress. Subsequent thermal treatments do not result in significant further degradation of the Si–SiO₂ interface (except for a loss of hydrogen), again in contrast to the case where the nitride films is deposited onto Si. Copyright © 2007 John Wiley & Sons, Ltd.     

Si-defect concentrations in heavily Si-DOPED GaAs: annealing-Induced changes-II

Isothermal annealing produces changes in the free carrier density, defect-induced localized vibrational mode (LVM) infrared absorption, microstructure as measured by transmission electron microscopy (TEM), and critical resolve shear stress of heavily Si-doped GaAs. The changes have been measured and correlated for three different Si concentrations for several annealing temperatures. The measurements reveal temperature dependent annealing-induced changes in several specific defect concentrations. The observations indicate the following behavior for two ingots with [Si] ≳ 2 × 10¹⁹ cm⁻¹³: (1) when the anneal temperature, T_A = 400°C, the concentration of Si_ga donors, as determined from LVM spectra decreases probably due to the generation of V_Ga defects followed by the formation of Si_Ga-V_Ga pairs. This change is responsible for observed decreases in carrier density and the large increase in yield stress. The yield stress shows a dependence of the form σ-σ_o ∝ [Si_Ga-V_Ga]^1/4. (2) When T_A = 500°C, the LVM spectra indicate that all of the observed Si defect concentrations change. The decrease in [Si_Ga] alone cannot explain the decrease in carrier density, and a previous suggestion that a new acceptor is required is confirmed. Both the LVM measurements and the shear stress indicate that only a small fraction of the [Si_Ga] reduction is by the formation of Si_Ga-V_Ga pairs. (3) When T_A = 700°C, a new acceptor is still required and the other experimental observations at T_A = 500°C are also still seen here. There is a large decrease in [Si_Ga] and [Si_As] observed for short anneal times which coincides with the formation of Si-rich extrinsic loops and the loop area/vol increases with [Si]. (4) When T_A > 700°C, all of the changes become smaller as T_A increases. For lower [Si] ~ 1.5 × 10¹⁸ cm⁻³, no significant annealing-induced changes are observed for any of the T_A given above.     

ArF excimer laser-enhanced photochemical vapor deposition of epitaxial Si from Si2H6: A simple growth kinetic model

Photolysis of Si₂H₆ using 193 nm radiation from an ArF excimer laser has been used to deposit homoepitaxial Si films in the temperature range of 250 to 350°C. Photolytic decomposition of Si₂H₆ generates growth precursors which adsorb on to a hydrogenated Si surface. A growth kinetic model is proposed based on single-photon 193 nm absorption by Si₂H₆, and chemical reaction of the photofragments as they diffuse to the sub-strate surface. With the laser beam positioned parallel to the Si substrate, the deposi-tion yield of solid Si from photo-excited Si₂H₆ is estimated to be 0.20 ± 0.04. Growth rates vary linearly with laser intensity and Si₂H₆ partial pressure over a range of 1–15 mJ/cm² · pulse and 5–40 mTorr, respectively, and epitaxial films are deposited when laser intensity and Si₂H₆ partial pressure conditions are such that the initial photofragment concentration is less than ~10¹³ cm⁻³.