Testability analysis and fault modeling of BiCMOS circuits

Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.This research was partially supported by the Department of National Defence of Canada, Academic Research Program, grant # 3705-921.     

Differential BiCMOS logic circuits: fault characterization anddesign-for-testability

Merged Current Switch Logic (MCSL) and Differential Cascode Voltage Switch Logic (DCVSL) are two common structures for differential BiCMOS logic family, that have several potential applications in high-speed VLSI circuits. This paper studies the fault characterization of these BiCMOS circuits. The impact of each possible single defect on the behavior of the circuits is analyzed by simulation. A new class of faults which is unique to differential circuits is identified and its testability is assessed. We propose a design-for-testability method that facilitates testing of this class of faults. Two different realizations for this method are introduced. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated     

Testable design of BiCMOS circuits for stuck-open fault detectionusing single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults     

浅析电力系统继电保护及故障检测

电力系统继电保护装置是电力系统安全稳定运行的重要基础,更是电力系统故障的第一道防线。随着近年来电力系统的加速发展,电力系统中出现的故障问题也日益严重。本文结合相关资料和文献分析电力系统继电保护及故障检测的重要作用,并对故障检测方法进行了简单介绍。     

Fault detection in resistive ladder network with minimal measurements

Testing of integrated circuits has now become a very important part of the semiconductor industry. Testing alone exceeds the cost of designing and manufacturing. So it is important to device new techniques to reduce the time and effort spent in testing [1]. The basic idea of the work done is to come up with a strategy to identify any fault in a resistive ladder network with minimal measurements, thereby reducing the testing time, efforts and cost [1]. Ideally the whole ladder circuit should act as a single segment and one or two measurements should detect the fault (location and type of fault). But since that is not possible we split up the big ladder network into segments which are as big as possible and at the same time giving good fault coverage. The ladder network was split into segments of different sizes. For each size scenario we analyzed the fault coverage. A detailed analysis for 2-step (4 resistors), 3-step (6 resistors) and 4-step (8 resistors) ladder networks were carried out and the results were found to be in favor of the 3-step ladder.     

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 μm, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e ^2.3(≈10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e^1.6(≈5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants     

Data-mining based fault detection

This paper presents a fault-detection method based on the phase space reconstruction and data mining approaches for the complex electronic system. The approach for the phase space reconstruction of chaotic time series is a combination algorithm of multiple autocorrelation and Г-test, by which the quasi-optimal embedding dimension and time delay can be obtained. The data mining algorithm, which calculates the radius of gyration of unit-mass point around the centre of mass in the phase space, can distinguish the fault parameter from the chaotic time series output by the tested system. The experimental results depict that this fault detection method can correctly detect the fault phenomena of electronic system.     

Backlash fault detection in mechatronic system

In this paper, a fault detection and isolation model based method for backlash phenomenon is presented. The aim of this contribution is to be able to detect then distinguish the undesirable backlash from the useful one inside an electromechanical test bench. The dynamic model of the real system is derived, using the bond graph approach, motivated by the multi-energy domain of such mechatronic system. The innovation interest of the use of the bond graph tool, resides in the exploitation of one language representation for modelling and monitoring the system with presence of mechanical faults. Fault indicators are deduced from the analytical model and used to detect and isolate undesirable backlash fault, including the physical system. Simulation and experimental tests are done on electromechanical test bench which consists of a DC motor carrying a mechanical load, through a reducer part containing a backlash phenomenon.     

多T接电缆混合线路故障测寻分析与探讨

随着城市电网地不断改造和电力电缆的广泛运用,高压电力电缆对城市电网的发展起着主导作用.电缆线路的增多和改造,也使T接电缆线路也不断出现,甚至出现一条电缆线路有多个T接电缆头.电缆一旦发生故障,寻找起故障点来十分困难,由于电缆应用规模的扩大、运行年限的增长,电缆故障也会越来越频繁,这就使得每年供电企业都要花费大量的人力物力,而且还将给企业带来难以估计的停电损失.因此,如何快速、准确、经济地找出电缆故障点,一直是供电企业跟施工单位探讨的首要问题.本文结合实际运行的多T接电缆线路故障实例,对测寻方法进行深入分析研究.     

Dynamic effects in the detection of bridging faults in CMOS ICs

Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors < T ₀, T ₁ >, in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T₀ initializes the faulty signal to a logic value different from the fault-free one produced by T ₁. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.     

Bounding fault detection probabilities in combinational circuits

This paper focuses on the problem of bounding fault detection probabilities in combinational circuits. Two algorithms, the complete cutting algorithm and the gate blocking algorithm, are presented that always produce true lower bounds on the detection probability of a fault. Both algorithms can be used to identify difficult-to-test faults and to quickly construct test sets for specific faults. Both algorithms have qualitative versions which provide insight into a circuit while avoiding arithmetic calculation. Both algorithms resulted from research in trying to determine the accuracy of the safety factor heuristic of Jacob Savir.This research was supported by a grant from the IBM Corporation.     

Multiple fault detection in fanout-free combinational networks

In this letter we show that an algorithm developed by Berger and Kohavi for generating minimal length fault-detection test sets for single permanent faults in fanout-free combinational logic networks also detects all possible multiple faults in the network.     

Efficient neighbor collaboration fault detection in WSN

In WSN(Wireless Sensor Network), the fault detection is the basic function of administration of WSN. In this paper, an optimized scheme of neighbor collaboration algorithm SM-WSN (Self-monitoring of Wireless Sensor Networks) is presented, which allows the SM-WSN having better performance in fault detection accuracy and network life time in WSN. It is better to make the WSN wide perspective and practicability in the future. At last, we compared our optimized scheme with SM-WSM, and the results show that the improved scheme is superior to the old algrorithm by simulation data.     

Multiple fault detection in two-level multi-output circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.     

人工智能在网络故障预警的应用

大数据时代,人工智能有了飞速发展。作为人工智能的重要分支之一,机器学习在网络运维有广泛的应用前景。本文结合网络故障预警工作,梳理了机器学习的主要算法模型,重点探讨了人工智能应用于故障预警的难点和关键技术：加权的样本采样、时序样本的特征值提取、使用随机森林模型和深度神经网络模型时的参数设置。     

Analysis of the metastable behaviour of a BiCMOS SR latch

The successful design of digital systems with asynchronous inputs requires careful management of timing relations. Flip-flops used as arbiters or synchronizers in these systems are under asynchronous control and thus can suffer from additional propagation delays due to metastable operation. These added delays lead to system malfunction. An analysis of metastable operation in BiCMOS SR flip-flops is presented. An analytical expression for the flip-flop resolving time is derived. Optimal sizing of the MOSFETs and BJTs is investigated analytically as well as by using SPICE simulation.     

Using immunology principles for fault detection

The immune system is a cognitive system of complexity comparable to the brain and its computational algorithms suggest new solutions to engineering problems or new ways of looking at these problems. Using immunological principles, a two- (or three-) module algorithm is developed which is capable of launching a specific response to an anomalous situation for diagnostic purposes. Experimental results concerning fault detection in an induction motor are presented as an example illustrating how the immune-based system operates, discussing its capabilities, drawbacks, and future developments.     

WSNs中基于数据匹配的分布式故障节点检测算法

针对无线传感网络的节点故障问题,提出一种新的分布式故障节点检测算法(DFDA).DFDA算法利用节点度信息估计节点对网络的重要性,并尽可能将节点度高的节点保存到网络中.通过比较节点间感测的数据,检测故障节点.为了增强检测的准确性,采用双重测定策略.仿真结果表明,相比于同类算法,DFDA算法提高了检测故障节点的精确度,并...