共查询到19条相似文献,搜索用时 156 毫秒
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提出了一种改进的高基CORDIC算法,显著减少了传统CORDIC算法的迭代次数,同时保持模校正因子依然是一个常数。该算法可用于旋转角度能事先确定的场合,例如FFT计算中的旋转因子乘法。所设计的复数乘法模块采用SMIC 0.13 μm工艺综合,结果证明,提出的结构相比通用复数乘法器节约了19.2%的硬件面积和29.1%的ROM存储器面积,同时SQNR大于83 dB,满足实际应用的要求。 相似文献
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CORDIC流水线结构因其高吞吐率及规整性,而很适合于FFT蝶形运算,但其缺点是耗资源多,本文从FFT中旋转因子固定不任意的特点出发,根据CORDIC基本旋转角度与缩放因子的对应关系和缩放因子之间的转换规律,对CORDIC流水线结构进行了改进,在蝶形运算速度不变的情况下,进一步减少所耗资源,在字长为16位的FFT中,每个旋转因子可用25位的控制序列来替代,从而使每个旋转因子的存储空间由32位减少到25位。 相似文献
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本文针对高速大规模FFT处理器的需求提出了一种基-4按时间抽取的双通道FFT算法的硬件结构,采用4块小容量双端口SRAM代替一块大容量SRAM的设计思路以及多级流水结构.此结构能同时从四个存储器中并行存取堞形运算的4个操作数和4个中间结果,极大的提高了处理速度.用CORDIC算法代替传统的乘法器,节省了大量的存放旋转因子的ROM表格和乘法器等硬件资源从而节省了电路面积,并设置了通道关断技术,进一步节省了功耗.经硬件验证,在系统时钟为100MHz时,1024点20位复数FFT计算时间平均为10us左右. 相似文献
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针对无线城域网中工作在2GHz~11GHz频带的IEEE802.16a标准,在实现其OFDM系统时提出一种高速而且经济的FFT处理器设计方案。设计中采用了Radix-4的频率抽取算法和并行的蝶型计算单元结构,而且将旋转因子预先存储在ROM中以提高处理器运行的速度。设计方案采用了单个蝶型运算单元以达到控制FFT处理器规模的目的。数据的输入与输出都共用一个存储器,这进一步节约了硬件资源损耗。 相似文献
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提出了FFT处理器的蝶形单元和地址发生器优化方案。通过改进Wallace树型加法器阵列结构,提高了蝶形单元乘法器的工作频率。提出了地址快速生成算法,该算法在快速产生地址的同时降低了读取旋转因子ROM的功耗。在Xilinx的Vertex-II系列FPGA上实现,该处理器可以稳定工作在150 MHz时钟下,速度满足设计指标。 相似文献
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在基于FPGA的FFT设计中,为了提高速度,本文提出了用移位寄存器存储旋转因子的方法,并且在Altera公司的Stratix系列的FPGA上做了验证。实验结果表明,该方法和普遍采用ROM做旋转因子存储器的方法相比,大幅提高了FFF的处理速度,能够更好地满足了FFT实时处理的要求。 相似文献
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针对无线城域网中工作在2GHz~11GHz频带的IEEES02.16a标准,在实现其OFDM系统时提出一种高速而且经济的FFT处理器设计方案。设计中采用了Radix-4的频率抽取算法和并行的蝶型计算单元结构,而且将旋转因子预先存储在ROM中以提高处理器运行的速度。设计方案采用了单个蝶型运算单元以达到控制FFT处理器规模的目的。数据的输入与输出都共用一个存储器,这进一步节约了硬件资源损耗。 相似文献
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The Fast Fourier Transform (FFT), Good-Winograd Fourier Transform (GWFT) and Winograd Fuorier Transform (WFT) are studied using residue arithmetic. High speed, high precision arithmetic is achieved by using arithmetic architecture and a plurality of small wordlength processors running is parallel. The disadvantage of this arithmetic is overflow intolerance. To insure that register overflow will not occur, in this modular structure, scaling policies for the three DFT's are derived and compared. 相似文献
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一种改进FFT算法在DSP上的实现 总被引:3,自引:0,他引:3
快速傅里叶变换(FFT)是数字信号处理中最为重要的工具之一。而在具体硬件实现中,如何减少内存引用次数,以降低功耗具有更重要的意义。论文以基2按时间抽取FFT为例,在深入分析旋转因子性质的基础上,提出了一种改进FFT算法可以减少旋转因子的引用次数,消除冗余的内存引用,并给出了在DSPVC5402平台上的实验数据。表明了该算法是切实有效的。 相似文献
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This paper proposes an optimized design of Discrete Hilbert Transform (DHT) processor using Complex Binary Number System (CBNS). The conventional implementation of DHT based on the “divide and conquer” approach involves two separate computational units for the real and imaginary parts, which requires a large silicon area and increases the path delay. In contrast, incorporation of CBNS in transformation techniques facilitates complex-valued signal processing through a single computational unit.The CBNS-DHT processor has been designed using the standard computational method of Fast Fourier Transform (FFT). The 2-D Systolic Array architecture along with a novel processing element has been proposed for CBNS based Complex-valued FFT (CFFT) and Inverse FFT (CIFFT) computations. The architecture of CBNS-CFFT/CIFFT has been extended to develop the CBNS-DHT processor on the Zynq-7000 family, XC7Z020-CLG484 FPGA platform. A comparative performance analysis of CBNS-DHT and Normal Binary Number System (NBNS)-DHT highlights the efficiency of CBNS-DHT in terms of VLSI parameters — silicon area, path-delay and memory utilization. CBNS-CFFT shows significant improvement in path delay and area consumption as compared to NBNS-CFFT for both Twiddle Factors and FFT size, which proves that CBNS based CFFT and DHT processor design is more efficient in terms of speed and area requirements. 相似文献
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As we enter the multi-core era, seeking methods to boost the performance of single-threaded applications remains critical. Achieving gains in processor performance by increasing the operating frequency has begun to meet more obstacles. However, significant performance improvements can be achieved by extending the capability of the processor with the addition of hardware support, which makes much more effective use of the available transistors. This paper presents a novel hardware support called, DistTree, to speed up processor performance. The DistTree hardware automates gather and scatter operations for applications with complex but predictable memory access patterns like the Fast Fourier Transform (FFT). With this hardware support integrated with a modern microprocessor (the Alpha architecture in our experiments), the FFT performance can reap a more than twofold increase when compared against the FFTW library, a state-of-the-art implementation. The DistTree hardware support enables the processor to spend the majority of processor cycles on executing the computations of an algorithm by reducing both the arithmetic and address computation overhead. Therefore, the performance of many single-threaded applications can be significantly increased. 相似文献
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基于CORDIC算法的高速基-4FFT处理器设计 总被引:1,自引:0,他引:1
针对目前数字信号处理中对高速傅里叶变换(FFT)的要求,进行了FFT算法研究,采用基-4算法来实现FFT处理器;设计了对称乒乓RAM结构,提高了FFT处理器的连续运算能力和运算速度;采用CORDIC算法代替复数乘法器,用移位加法实现了复数乘法运算,减小了系统资源占用,提高了系统速度,设计了防溢出控制结构,在不增加系统延时的基础上,提高了运算精度;采用AL-TERA公司FPGA进行了验证,仿真结果表明该FFT处理器最大工作频率可达168.86 MHz,能满足高速实时处理的要求。 相似文献
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针对当前数字信号处理领域对快速傅里叶变换应用的广泛需求,在对算法原理分析的基础上,给出了8点基-2按时间抽选FFT处理器的实现方案;并综合Xilinx xc3s1500系列芯片,通过Modelsim SE 6.0对程序进行仿真.实验结果表明,该处理器功能实现正确,并且具有较高的运算速度和精度. 相似文献