半绝缘GaAs热稳定性的研究

用霍尔效应、红外吸收和二次离子质谱方法对不同碳(C)含量的未掺杂半绝缘(SI)GaAs晶体的热稳定性进行了研究,发现EL2浓度([EL2])相近、碳浓度([C])不同的样品中,高碳含量的样品更易出现热转型.长时间热处理后,样品反型层中的载流子浓度超过了[C].这些结果表明,热处理过程中样品表面层不仅发生了施主中心EL2的外扩散,而且有新的受主中心产生.     

碲镉汞富汞热处理技术的研究

利用自行研制的垂直开管富汞热处理设备,研究了碲镉汞（HgCdTe）富汞热处理技术。经富汞条件下3000C热处理和后续的常规N型热处理,As掺杂的Hg1-xCd,Te分子束外延材料中的As原子已被激活成P型受主,As原子激活率同石英管封管热处理试验的结果基本一致。对包括3in Si基衬底在内的材料退火前后表面形貌进行的比较显示,样品表面形貌可得到很好的保护。研究结果表明,碲镉汞开管富汞热处理技术可用于第三代碲镉汞红外焦平面技术所需大面积多层掺杂异质外延材料的制备。     

组合设计可将PIN暗电流减小一个量级

贝尔实验室的研究人员发现一种晶片结合方法 ,可以将 Si/ In Ga As PIN光检测器中的暗电流降低一个量级。原先的粘接法是使 Si和 In Ga As晶片在 1～ 10 MPa压力 ,温度为 6 50°C下接触 ,这样在异界面产生一定压力。用新方法 ,首先要使两个晶片表面清洁 ,平整至原子允许范围内。即 X射线光电发射光谱显示表面碳、氧、氟和氯少于 0 .2单层 ,原子力显微镜检查测量均方根粗糙度小于 1.5nm。然后两表面在大约 5磅的重量下接触 ,彼此以范德瓦尔兹力键连。这种方法中只有在重量移开后 ,6 50°C的高温才开始退火 ,这样减少热扩散压力 ,使薄…     

非有意掺杂LEC SI GaAs中EL2分布特性的研究

测量比较了不同条件下热处理后非有意掺杂半绝缘(SI)LEC GaAs中EL2浓度及其分布的变化,为了分析这一变化,还检测了位错和As沉淀的分布。在实验结果基础上,对EL2分布不均匀性的起源和热处理改善EL2分布均匀性的机理进行了讨论。     

GaAs可饱和吸收体本征点缺陷的第一性原理计算与模拟

GaAs可饱和吸收体中的深能级缺陷(EL2缺陷)对其被动调Q性能有着重要的影响,因此有必要对EL2缺陷的微观结构及形成机理做进一步研究.用基于密度泛函理论的平面波赝势法首先对GaAs本征点缺陷(镓空位、砷空位、镓替代砷、砷替代镓、镓间隙、砷间隙)存在时的晶格结构进行优化,得到其稳定结构;然后通过各缺陷形成能的计算可得知...     

Temperature coefficients of grain boundary resistance variations in a ZnO/p-Si heterojunction

使用磁控反应溅射技术在Si(100)衬底上异质外延未掺杂的ZnO薄膜。制备得到的一些样品分别在氮气800°(S1)和氧气800°(S2)的条件下退火1个小时。对所有的样品进行了深能级瞬态谱(DLTS)和电流-电压(I-V)的测量。我们发现S1的晶界电阻具有正温度系数(PTC),而S2的晶界电阻具有负温度系数(NTC)。同时,S2的电流特性类似于普通的p-n结,而S1和未退火样品的电流特性呈现出双肖特基势垒的行为,这与理想的pn异质结模型的电流特性是矛盾的。结合DLTS的结果,揭示了在不同气氛下退火,导致了ZnO晶粒中的本征缺陷浓度和ZnO/p-Si异质结中的界面态密度的不同变化,影响了ZnO/p-Si异质结中的晶界势垒,产生了可调的电学特性,这个特性也许适合不同的应用。     

不掺杂半绝缘GaAs的补偿机制

用红外局域模方法测定了8个不同的不掺杂半绝缘GaAs样品的含碳(C_(As))量,发现碳浓度均小于5.20×10~(14)cm~3。由1.1μm红外吸收测量和400K霍尔系数测量推算出样品的净受主浓度N_A-No,结果表明所有样品的净受主浓度均大于碳浓度,对于切自晶体下半部的样品,差别可达一个数量级。因此,这些受主必定是碳以外的其他杂质缺陷造成的,其中硼(B_(As))可能是主要因素。     

表面氢化对SiC/金属接触的作用机理

提出 Si C表面氢化模型。以氢饱和 Si C表面悬挂键 ,减少界面态 ,从而制备理想的金属 /半导体接触 ,并将此模型用于 Si C器件表面处理 ,其优点在于避免了欧姆接触 80 0～ 1 2 0 0°C的高温合金 ,且肖特基接触整流特性较好。在 1 0 0°C以下制备了比接触电阻 ρc=5～ 8× 1 0 - 3Ω·cm2的 Si C欧姆接触和理想因子 n=1 .2 5～ 1 .3的肖特基结。与欧姆接触采用 95 0°C高温合金制备的 Si C肖特基二极管比较表明 ,表面氢化处理不仅能避免高温合金 ,降低工艺难度 ,而且能改善器件的电学特性。     

As压对LT-GaAs/AlGaAs多量子阱光学特性的影响

在衬底温度为 3 5 0°C的条件下 ,用分子束外延的方法 ,在不同的砷压条件下生长了 Ga As/Al0 .3Ga0 .7As多量子阱结构。 77K的荧光实验证明 ,砷压对样品的光学特性影响显著。认为砷压对低温多量子阱光学特性的影响是点缺陷随砷压的演化和能级间相互补偿的共同结果。通过优化砷压 ,样品的荧光峰的半峰宽减小到 3 me V,这是到目前为止所报道过的最窄的低温多量子阱的荧光峰。相应的垂直场光折变器件的电吸收为 60 0 0 cm     

Hg_(0.8)Cd_(0.2)Te光伏探测器热处理条件的确定

引言汞扩散法MCT的p—n结,是利用组分偏离化学计量比形成的。超过化学计量比要求的汞原子系间隙原子,起施主作用,缺少汞就造成晶格空位,成为受主。所以掌握热处理条件,使施主及受主浓度控制在成结所要求的范围,同时又能得到较佳的量子效率。     

热处理和淬火的未掺杂半绝缘LEC GaAs的均匀性

对未掺杂原生ＬＥＣＳＩＧａＡｓ单晶在５００～１１７０℃温度范围进行了单步、两步和三步热处理及淬火，研究了这种热处理对ＥＬ２分布的影响，并检测了位错和Ａｓ沉淀的变化。结果表明，６５０℃以上温度的热处理可以改善ＥＬ２分布均匀性，且在６５０～９５０℃温度范围的热处理中，ＥＬ２均匀性的改善与热处理后的降温速率无明显联系。此外，两步或三步热处理的样品中ＥＬ２分布甚至比单步热处理样品中更优。９５０℃以下的热处理和淬火对位错和Ａｓ沉淀无明显影响。但是１１７０℃热处理井淬火后位错密度增加大约３０％，Ａｓ沉淀消失。对经１１７０℃淬火的样品再进行８０Ｏ℃或９５０℃的热处理，Ａｓ沉淀重新出现。ＥＬ２分布的变化可能与点缺陷、位错和Ａｓ沉淀的相互作用有关。文中提出了这种相互作用的模型，利用该模型可解释不同条件热处理后ＥＬ２分布的变化。     

Reversible electrical properties of LEC GaAs

Undoped, low-pressure, liquid-encapsulated Czochralski GaAs can be reversibly changed from conducting (ρ ∼ 1Ω-cm) to semi-insulating (ρ ∼ 10⁷Ω-cm) by either slow or fast cooling, respectively, after a 5 hr, 950° C soak in an evacuated quartz ampoule. The semi-insulating wafers are very uniform and lead to tight threshold-voltage control in direct-implant MESFET’s. We have studied crystals in both states by temperature-dependent Hall effect, photoluminescence, IR absorption, mass spectroscopy, and DLTS. It is shown that donor and acceptor concentrations are typically more than an order of magnitude greater than the C and Si concentrations, which are both less than 3 × 10¹⁴ cm⁻³. The EL2 concentration remains relatively constant at about 1.0 × 10¹⁶ cm⁻³. Thus, the normal EL2-Si-C compensation model does not apply. The most likely explanation for the reversibility involves a delicate balance between native-defect donors and acceptors in equilibrium at 950° C, but with the donors dominating after a slow cool, and the acceptors after a fast cool. A consistent model includes a dominant donor at E_c 0.13eV, probably V_As – As_Ga, and a dominant acceptor at E_v + 0.07eV, probably V_Ga Ga_As. In this model, vacancy motion is very important during the slow cool. Such processes must be strongly considered in the growth of bulk, high-purity GaAs.     

Anomalies in annealed LT-GaAs samples

The annealing behavior of low temperature (LT)-GaAs layers was investigated using transmission electron microscopy, x-ray rocking curves, and H⁺ ion channeling. These data were compared to the Hall-effect and conductivity data obtained earlier on the same samples. An expansion of the lattice parameter above those observed for as-grown LT-GaAs layers was observed for the layers annealed at 300 and 350°C. No precipitation was observed in transmission electron micrographs for these annealing temperatures. Based on ion-channeling results, the As atoms (split interstitials) appear to be in the same position as found for the as-grown layers. A special arrangement of As split interstitials or out-annealing of gallium vacancies would be consistent with a decrease of the dominant acceptor in these layers and an increase in the lattice parameter. For annealing above 400°C, the lattice parameter decreased and in fact was found to achieve the substrate value at annealing temperatures of 500°C and above. The decrease in the lattice parameter above 400°C is related to the decrease of excess As antisite defects and As split interstitials in the formation of As precipitates.     

Fabrication of undoped semi-insulating InP by multiple-step wafer annealing

Recently, it was found that undoped semi-insulating InP can be reproducibly obtained by wafer annealing at 950°C for 40 h under phosphorus vapor pressure of 1 atm. Resistivity variation across the 50 mm diameter wafer after this annealing process, however, was in the range of 22.5–53.7%. In order to realize the fabrication of undoped semi-insulating (SI) InP with uniform electrical properties, multiple-step wafer annealing (MWA) procedure has been applied for the first time. It was found that two-step wafer annealing at 950°C for 40 h under phosphorus vapor pressure of 1 atm and at 807°C for 40 h under phosphorus vapor pressure ranging from 30 to 50 atm, was effective in improvement of the uniformity of the electrical properties of undoped SI InP. By the present MWA, the resistivity variation of 8–12% and the mobility variation of 2–4% could be obtained for 50 mm diameter wafers.     

Defect state assisted tunneling in intermediate temperature molecular beam epitaxy grown GaAs

Current transport in molecular beam epitaxy (MBE) GaAs grown at low and intermediate growth temperatures is strongly affected by defects. A model is developed here that shows that tunneling assisted by defect states can dominate, at some bias ranges, current transport in Schottky contacts to unannealed GaAs material grown at the intermediate temperature range of about 400°C. The deep defect states are modeled by quantum wells which trap electrons emitted from the cathode before re-emission to semiconductor. Comparison of theory with experimental data shows defect states of energies about 0.5 eVbelow conduction band to provide the best fit to data. This suggests that arsenic interstitials are likely to mediate this conduction. Comparison is also made between as-grown material and GaAs grown at the same temperature but annealed at 600°C. It is suggested that reduction of these defects by thermal annealing can explain lower current conduction at high biases in the annealed device as well as higher current conduction at low biases due to higher lifetime. Quenching of current by light in the as-grown material can also be explained based on occupancy of trap states. Identification of this mechanism can lead to its utilization in making ohmic contacts, or its elimination by growing tunneling barrier layers.     

Annealing temperature dependence of electric conduction and capacitance dispersion in nitrogen-implanted GaAs

The annealing behavior of nitrogen-implanted GaAs samples has been investigated by secondary ion mass spectroscopy, current-voltage (I-V) and capacitance-frequency (C-F) measurements. The I-V data show that the conductivity of as-implanted samples is dominated by variable-range hopping between defect states below 300 K. The implanted layer becomes highly resistive after annealing. The activation energy of the resistance is found to increase from 0.2 eV for as-implanted samples to 0.71 eV for 950°C-annealed samples. Significant capacitance dispersion is observed over frequency for implanted samples. Based on a proposed equivalent circuit, the high-frequency capacitance dispersion is shown to be the result of resistance-capacitance (RC) time constant effects. The increase of activation energy of the resistance can be explained by the creation of deep traps by high temperature annealing. Traps at 0.69 eV and 0.82 eV are detected for 700°C and 950°C-annealing, respectively.     

Effect of the annealing temperature on erbium ion electroluminescence in Si:(Er,O) diodes with (111) substrate orientation

The influence of the temperature of secondary annealing, stimulating the formation of optically and electrically active centers, on the erbium ion electroluminescence (EL) at λ≈1.54 μm in (111) Si:(Er,O) diodes has been studied. The diodes were fabricated by the implantation of 2.0 and 1.6 MeV erbium ions at doses of 3×10¹⁴ cm⁻² and oxygen ions (0.28 and 0.22 MeV, 3×10¹⁵ cm⁻²). At room temperature, the EL intensity in the breakdown mode grows with the annealing temperature increasing from 700 to 950°C. At annealing temperatures of 975–1100°C, no erbium EL is observed in the breakdown mode owing to the formation of microplasmas. The intensity of the injection EL at 80 K decreases with the annealing temperature increasing from 700 to 1100°C. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 35, No. 10, 2001, pp. 1224–1227. Original Russian Text Copyright ? 2001 by Sobolev, Emel’yanov, Nikolaev.     

红外吸收微区测量技术在半导体材料中的应用

本文采用微孔遮挡近红外吸收法，对厚度为０．５ｍｍ左右薄片半绝缘（ＳＩ）－ＧａＡｓ中深施主ＥＬ＿２进行了直接测量，使用微机控制自动测量系统对ＳＩ－ＧａＡｓ晶片中的ＥＬ＿２浓度进行了微区分布测量，利用显微傅里叶变换红外光谱测量技术对硅外延层厚度，硅中间隙氧、替位砍含量，硼、磷、硅玻璃中的硼磷含量及薄片ＳＩ－ＧａＡＳ中替位碳含量进行了ＦＴ－ＩＲ显微测量。实验结果为研究半导体材料的微区特性和均匀性提供了可靠的依据。     

Hemisphere-shaped silicon crystal wafers obtained by plastic deformation and preparation of their solar cells

Hemisphere-shaped crystal wafers can be prepared by the plastic deformation of Si crystal wafers. To obtain hemispherical Si wafers, graphite convex and concave dies were used. A Si wafer was set between dies and pressed at high temperatures. The Si wafer was pressed by an overweight of 200 N at various temperatures. The deformation regions in which well-shaped (100) and (111) wafers can be obtained by plastic deformation were determined using parameters of thickness and temperature. In order to demonstrate that the shaped wafers are of sufficiently high quality to be used in the preparation of devices, solar cells were fabricated using the hemispherical Si wafers pressed at 1,120°C and 1,200°C. The conversion efficiency of the hemispherical solar cells is 8.5–11.5%. It was clarified from the conversion efficiency of solar cells that the quality of the shaped crystal wafers can be improved by a proper annealing process. Thus, the hemispherical shaped wafers are of high quality to be used in the preparation of devices.     

A study of the process of decomposition of supersaturated GaAs:Fe solid solution by scanning probe microscopy

Using an atomic-force microscope, the decomposition of the supersaturated solid solution of iron-doped GaAs (GaAs:Fe) is studied. GaAs:Fe samples were obtained in the course of high-temperature diffusion of Fe into GaAs and subsequent annealing at a temperature by 200°C below the doping temperature. The measurements are performed for transverse cleavages along the cleavage planes of the GaAs:Fe wafers. It is shown that, during annealing of the GaAs:Fe samples, the supersaturated alloy decomposes with the formation of particles of the second phase from ∼50 nm to ∼1 μm in size. The particles of the second phase possess ferromagnetic properties at room temperature.