A weak-to-strong inversion mismatch model for analog circuit design

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I _s , threshold voltage V _T0, gamma γ, θ _o (dependent on mobility degradation and source-drain series resistances), and θ _e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23–61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.     

Design of power-controlled class1 Bluetooth CMOS power amplifier

In this paper, an RF power amplifier intended for class 1 Bluetooth application is designed using 0.35 µm CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35 μm CMOS process using a transistor with total width of 90 μm and 18 fingers and it shows excellent agreement with the f_t and S-parameter measurement data up to 6 GHz. The effects of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19 dBm with 33.7% PAE under 3.3 V supply. This amplifier has a power control feature; its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing.     

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages

A new curvature-correction technique for improving the temperature behavior of a CMOS voltage reference will be presented. The reducing of the temperature coefficient for the reference voltage will be realized compensating the nonlinear temperature dependence of the gate-source voltage for a MOS transistor working in weak inversion with the difference between two gate-source voltages. These MOS transistors are biased at drain currents with different temperature dependencies (PTAT and PTAT ^α, respectively), α parameter being selected to the optimal value for the implementing technology. The PTAT voltage generator will be designed using an original Offset Voltage Follower block, with the advantage of a reduced silicon occupied area as a result of replacing classical resistors by MOS active devices. SPICE simulation reports TC = 1.95 ppm/K for an extended temperature range, 273 K < T < 363 K, without considering the parameters spread. The circuit is compatible with low-power low-voltage designed, having a maximal power consumption of 0.4 μW for a minimal supply voltage of 1.1 V.     

5GHz0．18μm CMOS功率放大器设计

文中介绍了一个基于TSMC 0．18μm CMOS工艺,可应用于802．11a无线局域网标准的功率放大器设计。该电路采用三级全差分结构,驱动级采用电阻并联负反馈网络来保证稳定性。在3．3V电源电压下,增益为16dB,输出1dB压缩点为17dBm,电路功耗为0．8 W,效率为18．1%。芯片面积为1．2mm×1．1 mm。     

A cascode modulated class-E power amplifier for wireless communications

A cascode modulated CMOS class-E power amplifier (PA) is presented in this paper. It is shown that by applying a modulated signal to the gate of the cascode transistor the output power is modulated. The main advantage of the proposed technique is a high 35 dB output power dynamic range. The peak power added efficiency (PAE) is 35%. The concept of the cascode power control of class-E RF PA operating at 2.2 GHz with 18 dBm output power was implemented in a CMOS technology and the performance has been verified by measurements. The prototype CMOS PA is tested by single tone excitation and by enhanced data rates for GSM evolution (EDGE) modulated signal. Digital predistortion is used to linearize the transfer characteristic. The EDGE spectrum mask is met and the rms error vector magnitude (EVM) is less than 4° in the entire output power range.     

RF Power Performance of Asymmetric-LDD MOS Transistor for RF-CMOS SOC Design

This letter presents a new asymmetric-lightly-doped-drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic without any process modification. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added efficiency (PAE). The PAE is also improved by 16% at 10-dBm output power and 2.4 GHz. These significant improvements of RF power performance by this new MOS transistor make the RF-CMOS system-on-chip design a step further     

An efficient approach to the measurement and characterization of MOSFET capacitances

This article describes an improved methodology of estimation of the components of MOS transistor gate capacitances. It uses transistors on a test structure, which was designed for the purpose of a general characterization of CMOS technology and devices. The presented method is based on a comparison of the appropriate C–V characteristics of transistors of different gate dimensions. This allows efficient elimination of undesired parasitic capacitances of the measurement setup.     

An alternative to source degeneration of CMOS differential pair

This paper presents a method to extend linear range of conventional CMOS source-coupled pair with transistor polarised on saturation of strong inversion. The used principle is similar to the principle of source degeneration, but the additional device is horizontally added, in parallel with the input transistors, which overcame the constraints on common mode range and supply voltage and allow low voltage operation. SPICE simulations using 0.35 μm CMOS process and a bias current of 10 μA, show that for less than 1% of transconductance variation, the linear range is up to 0.35 V _pp in comparison to 0.1 V _pp for source-degenerated pair, and 0.01 V _pp for conventional differential pair, under the same biasing current and geometrical dimensions.     

Design challenges of a fully integrated 65 nm CMOS half cascode SFDS PA

This paper presents the measurement results of a wideband multi-standards fully integrated 65 nm CMOS-power amplifier (PA). This PA is based on a half stacked folded pseudo-differential structure (HSFDS) cascoded. This demonstrator is composed by only one stage. It provides a maximal gain of 10 dB at 2.2 GHz with a bandwidth at −3 dB (B _w -3 dB) of 43%. At 1.95 GHz, the maximal output power (P _max ) is 23.3 dBm with a power added efficiency (PAE) of 12%. The output power at 1 dB compression (OCP ₁ ) is 21 dBm. At 2.4 GHz, Pmax is 23 dBm with a PAE of 11.3%. At this frequency, the OCP1 is 20 dBm.     

S波段高效F类/逆F类GaN HEMT功率放大器设计

为了解决F类和逆F类（F-1类）功率放大器设计过程中受晶体管寄生参数影响,导致功放效率低以及输出匹配电路结构复杂的问题,提出了一种新型的输出匹配电路结构.首先,在直流偏置线中加入谐波调谐功能,避免单独设计谐波控制电路;其次,为满足F类和F-1类功放在器件本征漏极端所需的阻抗状态,匹配寄生参数呈现的封装端谐波阻抗,采用一段L型传输线结构代替传统的L-C集总元件寄生补偿方法;最后,由两段串联的传输线实现最优基波阻抗与50 Ω负载间的匹配.为验证方法的有效性,采用CGH40010氮化镓高电子迁移率晶体管（Gallium nitride high electron mobility transistor,GaN HEMT）器件,设计并加工了两款工作在2.4 GHz的F类和F-1类功放.测试结果显示:F类功放的峰值功率附加效率（power added efficiency,PAE）为75.5%,饱和输出功率为40.8 dBm;F-1类功放的峰值PAE为77.6%,饱和输出功率为40.3 dBm.该方法降低了电路复杂度和设计难度,可以较容易地补偿晶体管寄生参数,功放在高频工作时的效率得到提升,为利用GaN HEMT器件设计高效功放提供了一种可行的方案.     

基于谐波调谐的双频高效功率放大器设计

为了满足无线通信系统对低功耗双频功放的需求,分析高效功放的阻抗条件,提出了一种新型双频输出匹配电路,包括谐波控制电路和基波匹配电路两部分.首先,通过调谐晶体管的谐波阻抗减小漏极电压和漏极电流波形的重叠,从而提高功放的效率;其次,通过公式推导得出双频阻抗匹配电路参数,将晶体管在两个频率下的最佳基波阻抗匹配至50Ω.为验证...     

A wideband LC-VCO with small VCO-gain fluctuation for mobile DTV application

This paper presents a high linearity MOSFET-only transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-μm CMOS process. The measurement results show 18 dB improvement of the proposed version, and 65 dB HD3 can be achieved for a 2.1 MHz 700 mV_pp differential input. The static power consumption under 1-V power supply voltage is 183 μW. Measurement results demonstrate the agreement with theoretical analyses.     

基于CMOS工艺的高效，高耐用性RF LDMOS器件

Two types of RF LDMOS devices, specified for application in the driver stage and output stage of a power amplifier, are designed based on a modified CMOS process. By optimizing the layout and process, the output capacitance per unit of gate width is as low as 225 fF/mm. The driver stage and output stage devices achieve an output power of 44 W with a PAE of 82% and 230 W with a PAE of 72.3%, respectively(P3dB compression) at 1 GHz. Both devices are capable of withstanding extremely severe ruggedness tests without any performance degradation. These tests are 3-5 dB overdrive, 10:1 voltage standing wave ratio mismatch load through all phase angles, and 40% drain overvoltage elevation at a working point of P3dB.     

A 2.4 GHz high output power and high efficiency power amplifier operating at inductive breakdown in CMOS technology

In this paper, a novel CMOS power amplifier (PA) with high output power and power added efficiency is designed to operate in the avalanche region by increasing the supply voltage for the first time. With the X-parameter measurement based poly-harmonic distortion (PHD) behavioral model including the X^S and X^T terms, the simulation results can reveal accurate large signal characteristics of the whole PA at breakdown. The output power at 1-dB compression point of 30.2 dBm with 34.1% PAE at 2.4 GHz is obtained.     

SiC microwave power technologies

Two SiC transistors that are investigated for microwave power applications are the 4H-SiC static induction transistor (SIT) and the 4H-SiC metal-semiconductor field-effect transistor (MESFET). Ultrahigh frequency 4H-SiC SITs have demonstrated record-breaking pulsed power per package (900 W) with excellent associated power-added efficiency (PAE) of 78%. S band 4H-SiC MESFETs have shown a record power-density of 5.6 W/mm and 36% PAE, as well as 80 W continuous-wave (CW) power (1.6 W/mm), with an associated PAE of 38%. X-band MESFET power density of 4.3 W/mm was obtained for exploratory CW devices. These performance gains are afforded by the advantageous material properties of silicon carbide. SiC SIT technology offers many military system advantages including lower cost, lower weight, higher power and high temperature of operation and higher efficiency transmitters with minimal cooling requirements. SiC RF MESFET's and circuits are candidates for use in efficient linear transmitters for commercial and military communications.     

Pareto ANOVA analysis for CMOS 0.18 µm two-stage Op-amp

This paper presents a Pareto ANOVA analysis technique as an alternative way to analyze some selected optimization parameters in two-stage op-amp. Three input parameters and two output parameters based on standard L₂₇(3¹³) in Taguchi method have been chosen in this optimization methodology. The input parameters are selected based on the value of W/L ratio at three transistors which are transistor M8, M9 and M7. Two types of outputs have been aimed to optimize which are power dissipation and gain. This op-amp has been constructed by using CMOS technology 0.18 µm and the results have been verified by using a Mentor Graphic EldoSpice. From the analysis, it is found that level 16 has been chosen as an optimal combination produced by a Taguchi method. After this, Pareto ANOVA technique will be applied to analyze the effect of selected input parameters in achieving optimum gain and power of the two stage op-amp. The analysis showed that the value of W/L ratio at transistor M9 gives a major impact on power dissipation and value of W/L ratio at transistors M8 and M9 give a major impact on gain. This study also shows that Pareto ANOVA is an easier method to analyze circuit parameters.     

A fully integrated 23.2 dBm P1 dB CMOS power amplifier for the IEEE 802.11a with 29% PAE

A two-stage fully integrated power amplifier (PA) for the 802.11a standard is presented. The PA has been fabricated using UMC 0.18 μm CMOS technology. Measurement results show a power gain of 21.1 dB, a P_1 dB of 23.2 dBm and a P_SAT of 26.8 dBm. The PAE is 29% and it is kept high by means of several integrated inductors. These inductors present low-DC resistance and high Q characteristics. The inductors must include extra design considerations in order to withstand the high-current levels flowing through them, so that they have been called power inductors.     

High-frequency current instabilities in a silicon Auger transistor

In an Auger transistor formed from an Al-SiO₂-n-Si heterojunction with a tunneling-thin oxide layer we have investigated high-frequency instabilities of S-and N-type in the collector current which arise during tunneling injection of hot electrons from the metal into the semiconductor. An Auger transistor is a new type of device in which a metal-insulator heterojunction is used as the wideband semiconductor emitter and the base of the transistor is induced by an electric field in the form of a self-consistent quantum well for holes on the silicon surface. The electrons injected from the metal into the semiconductor with a high kinetic energy (greater than 1 eV) during impact ionization generate electron-hole pairs in the region of the base-collector junction. This disrupts the current balance of the transistor and leads to the appearance of an unstable current of S-or N-type in the collector characteristics (in a circuit with a common emitter). The nature of the instability is connected with the large current gain in an Auger transistor (α>1). Fiz. Tekh. Poluprovodn. 33, 1126–1129 (September 1999)     

Phase Transitions in the BiVO<Subscript>4</Subscript>-<Emphasis Type="Italic">n</Emphasis>PbO (<Emphasis Type="Italic">n</Emphasis> = 1, 2) System: Structural–Electrical Properties Relationships

In a general survey of nPbO-BiVO₄ compounds, interesting phases corresponding to n = 1: PbBiVO₅, and n = 2: Pb₂BiVO₆ are described. A phase transition has been unambiguously characterized for PbBiVO₅. The crystal structures were solved from twinned crystals at room temperature (α phase, triclinic, S.G. P-1) and at 530°C (β phase, monoclinic, C2/m). Powder neutron diffraction experiments confirmed these settings and both room-temperature (RT) and high-temperature (HT) refinements corroborated space group choices, clearing up a literature controversy about the centrosymmetry of the α phase, and identifying structural modifications occurring under the α → β transition. Cationic substitutions for V were tested and PbBi(V_1−x M _x )O₅ (M = P) solid solutions identified. Pb₂BiVO₆ (n = 2) is a compound showing several successive structural transitions, i.e., α → β → δ. Structures of α and δ forms have been previously described from powder diffraction data (x-ray and neutron). In this work, we have refined these structures from single-crystal data, and the resolution of the intermediate β form, so far unsolved, was possible through a stabilization thermal cycle; its complete structural understanding required a 4D formalism. Two new polymorphic phases, α′ and δ′, were obtained by substituting Mn or P for V; their structures are closely related to, respectively, the α phase at room temperature, and the δ phase at 680°C. Electrical conductivities of all structurally characterized compositions were investigated, and correlations were drawn between their conduction properties and structural characteristics. Conductivity properties measured under variable O₂ partial pressures for Pb₂Bi(V_0.75P_0.25)O₆ were interpreted as a mixed ionic–electronic (p-type) conduction mechanism.