2-1-1级联连续时间型ΣΔ调制器系统设计

高阶连续时间型ΣΔ调制器提供了一种有效的获得高分辨率、低功耗模数转换器的方法.提出了一种新型的2-1-1级联的连续时间型ΣΔ调制器结构.采用冲激不变法将离散时间型ΣΔ调制器变换为连续时间型ΣΔ调制器,利用Simulink对该调制器进行系统级建模和仿真,峰值信噪比达到105dB.分析了电路的非理想因素对调制器行为的影响,以获得90dB信噪比为目标确定了电路子模块指标.仿真结果表明,该结构能有效降低系统功耗,并验证了电路的可行性.     

改进型文氏桥混沌振荡器：建模、分析 与实验

通过引入二极管—电感并联网络实现了一种改进型文氏桥混沌振荡器。借助于二极管含寄生电容的分段线性模型,有效解决了该混沌电路的动力学建模问题。基于系统模型,研究了系统的平衡点及其稳定性,利用数值仿真和硬件实验手段,揭示并验证了随系统参数变化的动力学行为。结果表明,新提出的改进型文氏桥混沌振荡器有着简单的电路结构,存在混沌和周期等非线性动力学行为。     

CMOS analog/digital circuit of the hysteresis McCulloch-Pitts neuron for Ramsey numbers

A parallel algorithm for finding Ramsey numbers is presented where analog/digital CMOS circuits for the hysteresis McCulloch-Pitts binary neuron are described. The hysteresis McCulloch-Pitts binary neuron model is used in order to suppress the oscillatory behaviors of neural dynamics so that the convergence time is shortened. The proposed algorithm using the hysteresis McCulloch-Pitts binary neuron found five Ramsey numbers. The analog CMOS sigmoid circuit with variable gain controls has been fabricated and tested using the SAC data acquisition board interfaced with a TMS 32010 processor. Hysteresis can be implemented by the positive feedback in the fabricated CMOS analog circuit.     

Approximation of dynamical time-variant systems by continuous-time recurrent neural networks

This paper studies the approximation ability of continuous-time recurrent neural networks to dynamical time-variant systems. It proves that any finite time trajectory of a given dynamical time-variant system can be approximated by the internal state of a continuous-time recurrent neural network. Given several special forms of dynamical time-variant systems or trajectories, this paper shows that they can all be approximately realized by the internal state of a simple recurrent neural network.     

Automatic Tuning System for Integrator-Based Continuous-Time Filters

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.     

用于WCDMA系统的一种新型神经元MOS复数匹配滤波器

提出了一种新型神经元MOS复数匹配滤波器结构,用于实现WCDMA系统中复四相扩频调制信号的解扩运算.主要对关键电路进行了分析,与线性运算器件实现的复数匹配滤波器电路相比,具有结构简单的优点,大大降低了器件数目,HSPICE仿真结果验证了该电路结构的可行性.     

应用于助听器的连续时间滤波器设计

提出了一种采用电流控制传送器(CCCⅡ)构成的连续时间双二阶滤波器电路,该滤波器可以应用于助听器和其他的信号处理设备中,能对任意特定频率的信号进行放大或者衰减,易于实现大规模MOS电路的集成。理论分析和计算机仿真表明所提电路方案正确,是可行的。     

Third-order RLCM-four-elements-based chaotic circuit and its coexisting bubbles

This paper presents a new third-order RLCM-four-elements-based chaotic circuit, in which the memristor element is equivalently implemented by a diode-bridge cascaded with an inductor. Mathematical model is established and its equilibrium stability is analyzed. The dynamical properties of the memristive chaotic circuit are disposed by MATLAB numerical simulations and confirmed by breadboard experimental measurements. In particular, the antimonotonicity phenomena of coexisting periodic and chaotic bubbles are observed under some specified control system parameters and the evolutions of coexisting bubbles are exhibited with the variations of two control system parameters. The presented memristive chaotic circuit is very simple and only third-order but can emerge complex dynamics with chaos, period, coexisting bifurcation modes, and coexisting bubbles.     

Dynamic behavior analysis, color image encryption and circuit implementation of a novel complex memristive system

This paper is devoted to introduce a novel four-dimensional memristor-involved system and its applications in image encryption and chaotic circuit. The typical dynamical behaviors of the memristor-involved system are explored, such as chaotic phase potraits, Lyapunov exponent spectrum (LES), bifurcation diagram (BD) and complexity analysis. Then a color image encryption algorithm is designed. In this algorithm, the sequences generated by the four-dimensional memristor-involved system are used in scrambling and diffusion algorithm for three channels. The algorithm analysis results based on key space, key sensitivity, information entropy, histogram distribution, correlation coefficients, data loss and noise attacks indicate that the proposed algorithm can improve the security of the color image encryption algorithm. Finally, the memristor-involved chaotic circuit is implemented by using some discrete components. The experimental results of hardware circuit are consistent with the Multisim simulation results and the numerical simulation results. The research results have certain universality and portability, and can provide technical support for the subsequent analysis of other nonlinear circuits and the application of chaotic secure communication.     

Analog Hardware Implementation of Continuous-Time Adaptive Filter Structures

We have implemented a four-tap adaptive filter in a continuous-time analog VLSI circuit. Since an ideal delay is impossible to implement in continuous-time hardware, we implemented the delay line as a cascade of low-pass filters (called the gamma filter). Since many years of research in our lab has shown that the gamma filter outperforms the ideal delay line for a wide range of applications, the gamma filter should not be considered merely a crude approximation of the ideal delay line. We show measured results from an analog chip that solves the problem of system identification–identifying an unknown linear circuit from its input/output relationship. Furthermore, we believe that a cascade of all-pass filters (called the Laguerre filter) will potentially outperform the gamma. We have built an adaptive Laguerre filter and show that its measured convergence rate is superior to that of the gamma. Finally, rather than perform gradient descent on a multimodal error function to determine a single optimal time constant, we propose multi-scale realizations of these delay line structures.     

A Balanced Approach to Multichannel Blind Deconvolution

In some general state-space approaches to the multichannel blind deconvolution problem, e.g., the information backpropagation approach (Zhang and Cichocki 2000), an implicit assumption is usually involved therein, viz., the dimension of the state vector of the mixer is known a priori. In general, if the number of states in the state space is not known a priori, Zhang and Cichocki (2000) suggested using a maximum possible number of states; this procedure will introduce additional delays in the recovered source signals. In this paper, our aim is to relax this assumption. The objective is achieved by using balanced parameterization of the underlying discrete-time dynamical system. Since there are no known balanced parameterization algorithms for discrete-time systems, we need to go through a "circuitous" route, by first transforming the discrete-time system into a continuous-time system using a bilinear transformation, perform the balanced parameterization on the resulting continuous-time system, and then transform the resulting system back to discrete-time balanced parameterized system using an inverse bilinear transformation. The number of states can be determined by the number of significant singular values in the ensuing singular value decomposition step in the balanced parameterization.     

A 3-V continuous-time filter with on-chip tuning for IS-95

This paper describes a low-voltage channel selection analog front end with continuous-time low-pass filters and on-chip tuning for a receiver in an IS-95 cellular phone. The filters were realized as balanced seventh-order elliptical g_mC filters to achieve low current consumption. The transconductors were realized by using second-generation current conveyors (CCII) and resistors to achieve good intermodulation distortion performance. A novel CCII circuit topology was developed to fulfil the low supply-voltage requirement. The cutoff frequency tuning was implemented with capacitance matrices and a time-domain master-slave tuning circuit     

Bursting Hodgkin–Huxley model-based ultra-low-power neuromimetic silicon neuron

This paper presents a compact, ultra-low-power implementation of the bursting Hodgkin?CHuxley model-based silicon neuron. The Hodgkin?CHuxley model is a neuron imitation that consists of two calcium current channels, a potassium current channel and a leakage current channel. In the proposed architecture, the calcium and the potassium current channels have been implemented using a sigmoid-function structure, a log-domain filter, and a linear transconductor. Different neuronal signals can be generated by changing the value of the capacitor in the log-domain filter. The proposed silicon neuron is capable of generating four different outputs, namely, spiking, spiking with latency, bursting, and chaotic signals. Ultra-low-power consumption is achieved by current-reuse technique and subthreshold region operation of MOSFETs. The circuit is designed using 0.13???m standard CMOS process. The entire design uses 43 transistors, with a total power consumption of only 43?nW.     

An adaptive high-voltage protection and common-mode adjustment circuit for passive–active continuous-time sigma–delta ADCs

A digitally-programmable circuit is proposed to provide high-voltage protection at start-up, overload, and supply loss conditions in continuous-time passive–active sigma delta ADCs implemented in low-voltage nanometer CMOS technologies. The circuit optimizes the common-mode level at the input stage of the ADC enabling it to interface with input levels beyond its own supply voltage with no impact on device reliability or distortion levels, and minimum impact on area and noise performance, which provides maximum flexibility in the ADC usage. The proposed circuit along with the full ADC is implemented in a typical 65 nm CMOS technology.     

一种面向基于闪存的脉冲卷积神经网络的模拟神经元电路

该文面向基于闪存(Flash)的脉冲卷积神经网络(SCNN)提出一种积分发放(IF)型模拟神经元电路,该电路实现了位线电压箝位、电流读出减法和积分发放功能。为解决低电流读出速度较慢的问题,该文设计一种通过增加旁路电流大幅提高电流读出范围和读出速度的方法;针对传统模拟神经元复位方案造成的阵列信息丢失问题,提出一种固定泄放阈值电压的脉冲神经元复位方案,提高了阵列电流信息的完整性和神经网络的精度。基于55 nm 互补金属氧化物半导体(CMOS)工艺对电路进行设计并流片。后仿结果表明,在20 μA电流输出时,读出速度提高了100%,在0 μA电流输出时,读出速度提升了263.6%,神经元电路工作状态良好。测试结果表明,在0～20 μA电流输出范围内,箝位电压误差小于0.2 mV,波动范围小于0.4 mV,电流读出减法线性度可达到99.9%。为了研究所提模拟神经元电路的性能,分别通过LeNet和AlexNet对MNIST和CIFAR-10数据集进行识别准确率测试,结果表明,神经网络识别准确率分别提升了1.4%和38.8%。     

A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid 10.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6×0.57 mm~2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.     

A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators

Excess loop delay is one of the most critical non-idealities of continuous-time delta–sigma modulators as it leads to degradation of the signal-to-noise-ratio or even instability. A comprehensive study of the impact of excess loop delay on tunable continuous-time bandpass delta–sigma modulators using RC-resonators is performed in this paper, both analytically and by simulations. Moreover, a detailed analysis of the conventional compensation techniques for single-band continuous-time bandpass modulators as well as their adaptability to tunable bandpass modulators is performed. The results indicate that only tuning of the scaling coefficients is suitable to compensate for excess loop delay in high-speed tunable bandpass modulators. Based on this result, an approach to the compensation of excess loop delay is proposed which maps the poles of the noise transfer function (NFT) to almost ideal and thus stable positions. Excess loop delay equal to one clock cycle may thus be compensated while the available tuning range of the center frequency depends on the order and the out-of-band-gain of the NFT. A prototype implemented on a printed circuit board proves the feasibility of the proposed approach.     

特征神经网络收敛性分析

求矩阵的特征值与特征向量的问题是科学和技术中广泛遇到的问题，本文将实对称矩阵的特征问题转化为求非线性方程的解的问题，并建立了一连续时间动力学神经网络来探讨该非线性方程，在相当一般的条件下利用Ｌｙａｐｕｎｏｖ函数讨论了网络的稳定性与收敛性。     

An artificial intelligence approach to active filter synthesis

This paper deals with a novel active filter synthesis method using artificial intelligence (AI). The AI-based synthesis methodology uses original analog circuit representation performed by a Prolog backward-chaining inference mechanism. Circuit representation is specified as an analog circuit language to describe filter topologies, performance characteristics, and subcircuits. Synthesis is organized as a Prolog searching program based on backward-chaining strategy to transform input specifications into an appropriate filter structure. The Prolog program performs symbolic equation transformations to proper filter transfer characteristics. The proposed synthesis methodology has been developed for integrated continuous-time filter structures using operational transconductance amplifiers and capacitors to realize tunable and active C filters. A synthesis program has been implemented in Turbo Prolog on an IBM PC AT computer, and a filter example is presented demonstrating the use of the program.This paper was supported by the Ministry of Education of Poland Grant CPBP 02.14.     

A Digital Controller Assisted Flexible Auto-tuning Method for Continuous-time Filters

A novel auto-tuning method for the integrated continuous-time filter is proposed in this paper. On the one hand, an off-chip digital controller is adopted here to decrease the on-chip hardware as well as to increase the efficiency and the flexibility of the auto-tuning strategy. As a result, both the calibration and the programmability of the cut-off frequency can be realized by software, meanwhile some non-idealities of the circuit can also be compensated by software. On the other hand, the on-chip auto-tuning circuit is designed based on the master-slave architecture, where a novel and simple master circuit is adopted with digital input and output interfaces, thus providing convenient connections for the controller without the ADC or DAC devices. With the PCB technology, a 6th-order active-RC filter with the proposed auto-tuning method is also implemented to verify the validity and the flexibility of this method.