The bipolar transistor bucket-brigade shift register

An analysis of the bipolar transistor bucket-brigade shift-register operation is presented for comparison to other charge-transfer shift-register schemes. It is shown that incomplete charge transfer, the most important performance limiting effect for the charge-coupled device and the IGFET bucket brigade, is very small under most practical operating conditions for the bipolar transistor bucket brigade. In addition to charge loss due to finite transistor current gain h/SUB fe/ the next most important performance limitation comes from collector-emitter capacitance. It is shown that this collector-emitter capacitance leads to reduced analog time delay on transfer through the register and to signal attenuation effects similar to those resulting from incomplete charge transfer. Using the results of the analysis, experimental data reported by Sangster are discussed and a comparison of the advantages and disadvantages of the bipolar bucket-brigade register with the MOS charge-transfer registers is made.     

A new organization area image sensor with CCD readout through charge priming transfer

A new organization for an area image sensor with a wide dynamic range is proposed, in which an XY photodiode-MOS switch array is combined with an analog CCD readout shift register through a "charge priming transfer (CPT)" function. It is shown that use of the CPT makes the transfer of small signal charge from large capacitance vertical transport lines to the horizontal CCD strikingly efficient. The operating principle of the new device organization and some preliminary experimental results with a 404(H) × 256(V) element image sensor are reported.     

Incomplete transfer in charge-transfer devices

The authors present a general analysis of incomplete charge transfer in charge transfer devices. By using a lumped-charge model to characterize the dynamics of the charge transfer, they calculate /spl alpha/, the small-signal coefficient of incomplete transfer, in terms of single-device small-signal parameters. They show that three contributions to incomplete transfer are common to all charge-transfer shift registers: an intrinsic transfer rate contribution, an output conductance or feedback contribution, and a storage-capacitance modulation contribution. The analysis suggests that most relevant measurements necessary to characterize incomplete transfer can be made on a single cell of a shift register that has input and output diffusions. This allows transconductance etc., to be measured on a small-signal basis as a function of transfer current, from which one can calculate transfer efficiencies. An analysis of the influence of interface states which may be important for some charge transfer devices, is also included.     

Digital signal transfer in charge-transfer devices

The nonlinear properties of digital signal transfer through charge-coupled device and bucket-brigade shift registers are considered in terms of adjacent bit charge levels. A signal transfer efficiency is defined and shown to be a useful parameter for charge-transfer device shift register simulation. Approximate equations are developed for the worst case output bit levels and an approximate formula for the optimum input `fat' zero level, with respect to the worst case output signal `window', is obtained. The analysis includes only the intrinsic incomplete charge transfer properties of CTD's under square-wave clock pulsing conditions. Comparison of the theory and preliminary experimental results for CCD indicate good quantitative agreement.     

红外焦平面读出电路集成数字输出

为了实现红外焦平面数字化输出,设计了一种集成片上模数转换的焦平面读出电路,包括一个512512的读出电路单元阵列和列共享的逐次逼近寄存器型模数转换器(SAR ADC)。单元读出电路采用了直接注入(DI)结构作为输入级,输出的信号通过多路传输送到模数转换器。设计的逐次逼近型的模数转换器中的比较器采用的是由前置放大器、锁存器、自偏置差分放大器和输出驱动器组成的高速比较器,数模转换器(DAC)采用的是三段式的电荷按比例缩放和电压按比例缩放相结合的结构。在Cadence和Synopsys设计平台下对模拟和数字部分电路分别进行设计、仿真与版图设计。电路工艺采用GLOBALFOUNDRIES公司0.35 m CMOS 3.3 V工艺加工流片。测试结果显示SAR ADC有效位数为8.2位,转换频率超过150 k Samples/s,功耗低于300 W,满足焦平面100帧频以及低功耗的需求。     

Free charge transfer in charge-coupled devices

The free charge-transfer characteristics of charge-coupled devices (CCD's) are analyzed in terms of the charge motion due to thermal diffusion, self-induced drift, and fringing field drift. The charge-coupled structures considered have separations between the gates equal to the thickness of the channel oxide. The effect of each of the above mechanisms on charge transfer is first considered separately, and a new method is presented for the calculation of the self-induced field. Then the results of a computer simulation of the charge-transfer process that simultaneously considers all three charge-motion mechanisms is presented for three-phase CCD's with gate lengths of 4 and 10 µ. The analysis shows that while the majority of the charge is transferred by means of the self-induced drift that follows a hyperbolic time dependence, the last few percent of the charge decays exponentially under the influence of the fringing field drift or thermal diffusion, depending on the design of the structure. The analysis shows that in CCD's made on relatively high resistivity substrates, the transfer by fringing-field drift can be very fast, such that transfer efficiencies of 99.99 percent are expected at 5- to 10- MHz bit rates for 10-µ gate lengths and at up to 100 MHz for 4-µ gate lengths.     

高重频脉冲激光引起CCD视频中的动态次光斑现象研究

研究分析了CCD光电转换后信号电荷的传输过程以及激光高亮度的特点.认为高亮度的激光容易使感光二极管饱和,从而使光生电荷不通过读出脉冲控制而直接溢出至垂直CCD中,形成溢出信号电荷包;高亮度激光在垂直CCD内的漏光信号较强,从而直接在垂直CCD中形成漏光信号电荷包.溢出信号电荷包和漏光信号电荷包不依赖读出脉冲而出现于垂直CCD中,它们叠加在一起称之为次信号电荷包.次信号电荷包,经过垂直CCD的耦合转移动作,就形成了区别于激光主光斑的次光斑.研究中对次光斑的间距及循环移动的规律给出了定量的分析.次光斑的间距由CCD的转移频率和激光的重频频率所决定.而相邻帧中,主光斑与次光斑的间距有周期性的变化,从而造成了CCD输出视频中的次光斑循环移动.这种变化是由CCD垂直扫描周期被激光脉冲间隔时间整除后的余数所决定的.     

Charge-coupled devices with compensated charge transfer

It was shown that charge-transfer inefficiency in charge-coupled devices can effectively be compensated by doubling the number of unit cell required for charge transfer. An empty cell should follow each charged one, and charge readout in the output unit is performed via the summation of the charges on every pair of such cells.     

Step and frequency responses of c.t.d.s with nonuniform transfer inefficiency

General models for the small-signal step and frequency responses of charge-transfer devices with nonuniform inefficiency are derived. The case when the transfer inefficiency becomes position-dependent due to a nonuniform distribution of the background charge along the register is experimentally investigated using bucket-brigade delay lines as test vehicles.     

Performance limitations of the IGFET bucket-brigade shift register

The IGFET bucket brigade in integrated circuit form is a particularly simple structure for implementing dynamic charge transfer shift registers. Experimental and analytical studies show that incomplete charge transfer is an important limitation of register performance leading to signal degradation. This sets an upper limit to the clock frequency and to the number of stages in the register. The effects leading to incomplete charge transfer include: 1) the finite rate at which charge moves from one capacitor to the next through the IGFET transconductance; 2) the reduction in transfer rate (due to IGFET output conductance) when part of the charge has already been transferred to the drain; and 3) the loss of charge to interface states. The relative importance of these effects depends on device structure, clock frequency, clock voltage amplitude, and waveform. Under most operating conditions the IGFET output conductance contribution is most important, and the best results were obtained with a structure that minimized the effect. Experimental data show that p-channel registers in 31-bit strings can be operated satisfactorily to clock frequencies in excess of 5 MHz, and that by appropriate register design significantly better performance should be possible.     

Analog capacitance ROM with IGFET bucket-brigade shift register

A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.     

Oxide transfer storage for a diode array scan converter

A method is described for producing long-term storage on a diode array target scan converter. This is achieved by a simple target pulsing sequence which causes a change transfer from the diodes to the adjacent oxide. High-resolution storage of single-shot subnanosecond events can be obtained with storage times, in continuous readout, of greater than 30 min.     

An analog CCD reformatting memory employing two-dimensional charge transfer

An analog CCD reformatting memory has been designed and fabricated using an n-channel double level polysilicon gate process. This unique CCD structure employs two-dimensional charge transfer cells in a 32/spl times/32 element array which is accessed by means of integrated CCD demultiplexer and multiplexer structures resulting in greater dynamic range than observed in previous line-addressed designs. The design and operation of this structure are discussed, and examples of applications in analog signal processor architectures are described.     

A memory system based on surface-charge transport

The surface-charge transistor (SCT) is an integrated-circuit element and involves a new concept for controlling the transfer of stored electrical charge along the surface of a semiconductor. The experimental transient response of a large-geometry SCT is presented. Linear high-density arrays of surface-charge transistors may be utilized to form digital or analog shift registers. The experimental performance of a 14-bit shift register, which has been operated in both these modes, is given. By forming these units in a serpentine fashion, charge (information) may be transported back and forth between refresh circuits to form an array of cells. An experimental circuit of this type is presented. Using these techniques a digital serial memory of high density may be constructed. Using standard metalization linewidths and tolerances a cell size of 2 mil/SUP 2/ per bit is shown to be feasible.     

Alpha-particle-induced charge transfer between closely spaced memory cells

A detailed analysis of various mechanisms involved in α-particle-induced charge transfer between two trench-type DRAM cells is reported. An analytical model has been developed to describe the charge-transfer mechanisms. The charge-collection process consists of two phases. In the first phase, funneling is tile dominant mechanism, and the axial current is calculated based on the drift component. In the second phase, the structure behaves similarly to a bipolar transistor, and both the drift and diffusion components contribute to the charge transfer. A discussion of the dependence of the charge transfer on stored charge, cell separation, charge in the α-particle track, and the substrate doping concentration is presented.     

Design and testing of rapid single flux quantum shift registerswith magnetically coupled readout gates

Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO_x/Nb Josephson-junction process at a critical-current density of 1000 A/cm². The power dissipation per bit is 3 μW     

Analog performance limitations of charge-transfer dynamic shift registers

Charge transfer dynamic shift register operation is described and a linearized analysis presented to relate the charge transfer properties to the performance of an n-stage register. An approximate small signal equivalent circuit is also derived to illustrate the similarities to a matched transmission line and the reactive and resistive elements of the line are related to charge transfer and loss characteristics of each stage of the register. The results are expected to be applicable to charge coupled devices and shift registers based on bucket brigade electronics.     

A new accelerated transfer method for the CPD image sensor

A new charge transfer method for the CPD image sensor is proposed. In this method a high transfer speed is achieved with the use of an accelerated charge priming transfer (CPT) coupler, which consists of the array of the conventional CPT's and inverter amplifiers. This constitution strikingly increases the speed as well as the efficiency of the charge transfer from the vertical transport lines with large capacitance to the horizontal buried-channel charge-coupled (BCCD) shift register. Under a high transfer efficiency of more than 98 percent, a short transfer time less than 1 µs has been attained, independently of the signal charge magnitude.     

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper,a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor transistor (CMOS) technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit (ROIC) with a larger array, such as 320×240 size array.     

Charge-transfer filtering

Linear discrete-time (sampled-data) filters can be implemented in monolithic form on an MOS chip using a variety of recently developed and newly emerging techniques without requiring analog-to-digital conversion. An analog signal sample can be represented by an isolated quantity of charge and such packets of charge can be stored, transferred, and manipulated in other ways to perform signal processing operations. Best known of these techniques is the use of a charge-coupled device (CCD) to operate as an analog shift register. A simple modification of the CCD shift register allows the realization of transversal filters. Other techniques can implement recursive filter operations offering a great flexibility for filter design. The possibilities and limitations of charge-transfer filtering are reviewed and examined.