Optimizing synchronization in multiprocessor DSP systems

This paper is concerned with multiprocessor implementations of embedded applications specified as iterative dataflow programs in which synchronization overhead can be significant. We develop techniques to alleviate this overhead by determining a minimal set of processor synchronizations that are essential for correct execution. Our study is based in the context of self-timed execution of iterative dataflow programs. An iterative dataflow program consists of a dataflow representation of the body of a loop that is to be iterated an indefinite number of times; dataflow programming in this form has been studied and applied extensively, particularly in the context of signal processing software. Self-timed execution refers to a combined compile-time/run-time scheduling strategy in which processors synchronize with one another based only on interprocessor communication requirements, and thus, synchronization of processors at the end of each loop iteration does not generally occur. We introduce a new graph-theoretic framework based on a data structure called the synchronization graph for analyzing and optimizing synchronization overhead in self-timed, iterative dataflow programs. We show that the comprehensive techniques that have been developed for removing redundant synchronizations in noniterative programs can be extended in this framework to optimally remove redundant synchronizations in our context. We also present an optimization that converts a feedforward dataflow graph into a strongly connected graph in such a way as to reduce synchronization overhead without slowing down execution     

能实现多处理器DSP设计的集成开发环境Virtuoso 4.0IDE

包括多处理器DSP RTOS、图形化调试工具及多任务网络主机服务器等     

Fully static multiprocessor array realizability criteria forreal-time recurrent DSP applications

The paper considers real time implementation of recurrent digital signal processing algorithms on an application-specific multiprocessor system. The objective is to devise a periodic, fully static task assignment for a DSP algorithm under the constraint of data sampling period by assuming interprocessor communication delay is negligible. Toward this goal, the authors propose a novel algorithm unfolding technique called the generalized perfect rate graph (GPRG). They prove that a recurrent algorithm will admit a fully static multiprocessor implementation for a given initiation interval if and only if the corresponding iterative computational dependence graph of this algorithm is a GPRG. Compared with previous results, GPRG often leads to a smaller unfolding factor α_GPRG     

Fuzzy logic arbiters for multiple-bus multiprocessor systems

This paper describes and evaluates the use of fuzzy logic arbiters for multiple-bus shared memory multiprocessor system. Multiple-bus systems allow multiple and simultaneous bus transfer in addition to a high degree of fault tolerance. In such systems, arbiters are used to resolve conflicts to system resources, which are the shared memory modules and the buses. Typically, these conflicts are resolved by using two-stage arbitration schemes that employ policies such as random choice, daisy chaining, round-robin, etc. A new way of implementing these arbiters is the use of fuzzy logic to resolve resource request conflicts based on the system state and performance variables. This paper describes a new technique for implementation of fuzzy logic in the system arbiters and presents a simulation program that evaluates the system performance. The program is coded in such a way as to accommodate any arbitration scheme, from which the fixed priority and fuzzy priority have been implemented. Parameters affecting multiple-bus system performance are considered and used as inputs to the fuzzy arbiters. The inputs are fuzzified by using appropriate membership functions, and rules have been defined in such a way as to increase and distribute evenly the acceptance probability of each processor in the system. Results from the simulation program using a prioritized arbitration scheme are compared against other published results and show very close agreement. Furthermore, results show an increase in the acceptance probability of the processors using fuzzy arbiters.     

Hard-disk based development systems with multiprocessor emulation

An entirely new series of hard-disk based development systems is introduced, with particular reference to multiply in-circuit emulation stations for multi-user or multiprocessing configurations.     

Reliability modelling and analysis of multiprocessor systems

This paper presents symbolic analytical models to evaluate various reliability measures of a multiprocessor system (MPS). The most commonly used interconnection networks for MPSs, viz. multibus, crossbar and multiport memories, are considered. Simple expressions for system reliability, threshold reliability and multiprocessing reliability are obtained by modelling the MPS as a t-out-of-s system. The methods used are efficient and easy to implement on a computer. Direct numerical computations are also easy. These expressions are also applicable to systems with components of non-identical statistical properties. System availability can be also evaluated by the reliability study.     

Synthesis of application-specific multiprocessor systems including memory components

Heterogeneous systems have the potential to achieve enhanced performance as well as cost-effectiveness over homogeneous systems when the application domain is known since they can match the problem structure more closely. A formal design method, SOS, has been developed which can be used to synthesize optimal heterogeneous systems for given applications. The method involves creation of a Mixed Integer-Linear Programming (MILP) model and solution of the model. In this paper, first we show how to apply the method to application-specific systems with bus-style interconnection between the processors. We further demonstrate how to extend the method to deal with memory costs explicitly. Several experiments were performed with the original as well as the extended MILP models. These results indicate that it is important to include memory costs explicitly at design time.     

Recent advances in DSP systems

Some of the advances that have contributed to the realization of communication systems with programmable digital signal processors (DSPs) are described. DSP architectures are examined, covering the performance improvements resulting from advances in circuitry as well as in architecture. Architectural advances discussed are parallel processing, function generation, integrating analog circuits, and sigma-delta analog-to-digital conversion. DSP applications to high-speed modems, trellis-coded modulation, and echo cancellation are examined. The DSP implementation of a V.32 modem is described     

A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP

An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PEs are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 200-mm², 0.25-μm CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply     

Energy efficient semi-partitioned scheduling for embedded multiprocessor streaming systems

In this paper, we study the problem of energy minimization when mapping streaming applications with throughput constraints to homogeneous multiprocessor systems in which voltage and frequency scaling is supported with a discrete set of operating voltage/frequency modes. We propose a soft real-time semi-partitioned scheduling algorithm which allows an even distribution of the utilization of tasks among the available processors. In turn, this enables processors to run at a lower frequency, which yields to lower energy consumption. We show on a set of real-life applications that our semi-partitioned scheduling approach achieves significant energy savings compared to a purely partitioned scheduling approach and an existing semi-partitioned one, EDF-os, on average by 36 % (and up to 64 %) when using the lowest frequency which guarantees schedulability and is supported by the system. By using a periodic frequency switching scheme that preserves schedulability, instead of this lowest supported fixed frequency, we obtain an additional energy saving up to 18 %. Although the throughput of applications is unchanged by the proposed semi-partitioned approach, the mentioned energy savings come at the cost of increased memory requirements and latency of applications.     

Efficient design of multiprocessor systems for fault detection andlocation

The problem of constructing checks is one of the most important problems in designing algorithm-based fault tolerant (ABFT) systems. The authors establish a systematic approach to the design of checks of an ABFT system based on linear codes over real numbers, which is more efficient in implementation than previous methods, and develop some new upper bounds on the number of checks required by a given ABFT system, which are less than or equal to those available     

Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emerging area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance and yield improvement techniques. Fault tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault tolerance at work in these multiprocessor systems. These precepts are useful to then present certain techniques that will incorporate fault tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques.     

Real‐time causal message ordering in multimedia systems

Messages that are sent to and received by multiple sites need to have a consistent order imposed by all sites. Causal ordering allows the cause and effect relations of messages to be maintained. This paper presents an algorithm that ensures that multimedia data with real‐time deadlines are delivered to the application layer in causal order. The algorithm is designed to ensure that any message that arrives at a destination site before its deadline will be delivered to the application before the message expires. In addition, by focusing on a form of causal ordering violations caused by “the triangle inequality”, this algorithm has a low overhead with respect to the amount of information that must be appended to each message. This revised version was published online in June 2006 with corrections to the Cover Date.     

Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems

A methodology for the hierarchical partitioning and mapping of digital signal processing (DSP) tasks to heterogeneous local cluster based network of very large scale integration (VLSI) processors is presented. The goal is to achieve rapid prototyping of VLSI DSP systems. The high level partitioning issues of DSP task graphs and the proposed metrics to guide the partitioning process are described in this paper. Partitioning tominimize power inefficiency in the DSP system is one important metric addressed by this work, since low power signal processing is paramount to new portable and high density multi-chip module (MCM) DSP systems. The application of theRatio Cut Partitioning approach to DSP graphs is explained. We illustrate our results with examples and show how the final partitions vary depending upon the target architecture to meet rapid prototyping requirements. We compare our approach with known techniques and show that it works much better for our target applications.     

Partitioning of even networks for improved diagnosability[multiprocessor systems]

A partitioning property of even interconnection networks is presented. This property is based on the Hadamard matrix combinatorial structure which is used to partition the network into identical spheres. A semidistributed diagnosis algorithm helps to identify faulty components (nodes/links) in each sphere. Using the diagnosis result of each sphere on a global level, the overall diagnosability or even networks is improved drastically over previous results. This partitioning and diagnosis scheme can be used for almost any network that has some group-theoretic representation, including the binary hypercube     

Parameterized dataflow modeling for DSP systems

Dataflow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of dataflow, termed synchronous dataflow (SDF), that offers strong compile-time predictability properties, but has limited expressive power, has been studied extensively in the DSP context. Many extensions to synchronous dataflow have been proposed to increase its expressivity while maintaining its compile-time predictability properties as much as possible. We proposed a parameterized dataflow framework that can be applied as a meta-modeling technique to significantly improve the expressive power of any dataflow model that possesses a well-defined concept of a graph iteration, Indeed, the parameterized dataflow framework is compatible with many of the existing dataflow models for DSP including SDF, cyclo-static dataflow, scalable synchronous dataflow, and Boolean dataflow. In this paper, we develop precise, formal semantics for parameterized synchronous dataflow (PSDF)-the application of our parameterized modeling framework to SDF-that allows data-dependent, dynamic DSP systems to be modeled in a natural and intuitive fashion. Through our development of PSDF, we demonstrate that desirable properties of a DSP modeling environment such as dynamic reconfigurability and design reuse emerge as inherent characteristics of our parameterized framework. An example of a speech compression application is used to illustrate the efficacy of the PSDF approach and its amenability to efficient software synthesis techniques. In addition, we illustrate the generality of our parameterized framework by discussing its application to cyclo-static dataflow, which is a popular alternative to the SDF model     

Method of simulation the asymmetric memory access for solving synchronization problems in multiprocessor systems

A method and algorithm for accelerating the simulation in the route of the joint hardware-software verification of Multicore systems-on-chip (SoC) are developed. An approach with the peculiarity of simulating the asymmetric memory access, which provides the solution for the synchronization problem in multiprocessor systems with a considerable increase in performance as compared to the simulation of the RTL model, is proposed.     

分布式悬挂物管理系统的知识处理研究

悬挂物管理系统是航空火控系统的重要组成部分，将知识处理引入悬挂物管理系统并作了扩展，建立了分布式悬挂物管理系统的知识处理算法，并实现了分布式悬挂物管理系统的知识传输和可视化，从而使作战飞机达到交互性、可扩展性、可配置性，力求最大限度地提高作战效能。     

Stochastic ordering results for consecutive k-out-of-n:F systems

A linear (circular) consecutive k-out-of-n:F system is a system of n linearly (circularly) ordered components which fails if and only if at least k consecutive components fail. We use recursive relationships on the reliability of such systems with independent identically distributed components to show that for any fixed k, the lifetime of a (linear or circular) consecutive k-out-of-n:F system is stochastically decreasing in n. This result also holds for linear systems when the components are independent and not necessarily identically distributed, but not in general for circular systems.     

Low-cost multiprocessor system

The letter presents a multiprocessor system particularly advantageous in tightly coupled structures. The procedure is based on the fact that the microprocessor CPUs actually interact with the memory and I/O devices during a small fraction of the clock cycle. Conflicts in the memory bus access are avoided by a simple clocking and enabling method.