16位流水线ADC系统级建模及仿真

基于MATLAB/Simulink的平台,设计并实现了16bit 100M流水线模数转换器(ADC)系统仿真的理想模型.在充分掌握流水线ADC整体结构基础上,对其基本模块进行建模,充分考虑并加入电路的非理想特性和噪声,使整个系统模型接近实际电路.在输入信号为40MH2,采样时钟频率为100MHz时,分别对理想模型和加入非理想因素后的模型进行仿真比较,得到各项性能指标.对实际电路的设计具有一定的借鉴作用.     

多参数流水线A/D转换器的系统模型设计与仿真

提出了一种多参数流水线A/D转换器(ADC)的系统模型,该模型充分考虑了实际电路中存在的热噪声和各种非理想特性,通过对一个12位流水线ADC进行仿真,给出了在理想和各种非理想特性影响下系统性能的变化。得出的结果能有效地指导实际电路设计。     

2 GHz采样连续时间ΣΔ ADC高层次建模

宽带连续时间ΣΔADC被大量应用于无线通信及其他领域。设计采用3阶连续时间系统架构,包含3级RC环路滤波器和4位内部量化器,采样时钟频率为2GHz。通过引入半个时钟周期延时来改善环路异步问题,以补偿环路延时对性能的影响。对连续时间ΣΔADC的非理想因素,如运放有限带宽、有限增益、积分器时常数变化、DAC失配、比较器失调、时钟抖动等,进行建模,通过大量系统仿真,得出各个非理想参数指标,在100 MHz带宽内、2GHz采样频率下,ΣΔADC的SNDR为76.8dB,动态范围为77dB。     

基于MATLAB的新型Pipeline ADC的建模和仿真

在MATLAB/Simulink的平台上,设计并实现了一种新的10 bit Pipeline ADC的系统仿真模型.针对2 bit,共9级的结构的精度不足以及4 bit首级结构的功耗较大的特点,提出了一种首级3 bit,共8级的结构.这种结构可以实现精度和功耗的平衡.经过系统仿真,在输入信号为10 MHz,采样时钟频率为40 MHz时,系统最大的SNR=60.36 dB,SFDR=82.177dB.创建的系统模型可为ADC系统中的误差和静态特性研究提供借鉴.     

2.125～3.125GHz高速CMOS锁相环电路设计

针对数模混合结构的电荷泵锁相环电路,建立了系统的数学模型,确定了电荷泵锁相环的系统参数,提出一种能够有效消除时钟馈通、电荷注入等非理想特性影响,并具有良好电流匹配特性的电荷泵电路,以及一种中心频率可调的压控振荡器电路。电路采用SMIC 0.18μm CMOS工艺模型,使用Spectre进行仿真。结果显示,整个锁相环系统的功耗约为40 mW,输出时钟信号峰-峰值抖动为21 ps@2.5 GHz,单边带相位噪声在5 MHz频偏处为-105 dBc/Hz。     

流水线ADC的系统级仿真

应用模拟电路自顶向下的设计思想，用MATLAB建立了一个流水线型模数转换器的行为模型，从而可以有效确定系统结构及相关模块参数。为了对实际电路有较好的指导作用，充分考虑了电路的非理想特性和噪声。最后通过设定一个分辨率为10bit，采样频率为80MHz，1．5bit／级的经典流水线型数模转换器模型的非理想参数值和噪声参数，对ADC模型的主要性能参数进行了仿真计算。     

三阶级联Sigma-Delta调制器设计

介绍2-1级联的三阶调制器设计结构，讨论信号比例系数、积分增益系数和电路非理想特性对调制器系统的性能影响：运用SIMULINK对调制器建模并仿真，模型中考虑．开关电容积分器的非理想因素对整个调制器的影响．并通过调整信号比例和积分增益系数来确定调制器性能和电路要求。当采样率为125和时钟频率2．50MHz时．该模型结构得到93dB的信噪失真比，可应用于实际的电路系统。     

连续时间Sigma Delta ADC设计和非理想因素分析

文章设计了一个用于物联网模拟基带的、低压、低功耗、宽带、连续时间Sigma Delta ADC,特别是对各种非理想因素（时钟抖动,环路延时,运放有限增益和带宽,比较器offset,DAC失配等）,基于matlab和simulink等工具进行了系统级仿真并得到各种非理想因素对系统性能的影响。电路架构采用3阶3bit前馈加反馈结构,电源电压1.2V,输入信号带宽为16MHz,过采样率为16,采样频率为512MHz。测试结果显示,SNR为60dB,SNDR为59.3dB,总功耗为22mW。     

Delta Sigma调制器非理想因素建模

系统构建并研究了开关电容积分器DeltaSigma调制器非理想因素行为级模型.重点实现一种运放非线性直流增益模型,仿真表明它更有效反映奇次谐波失真,为保证模型真实性,综合考虑调制器其他非理想因素,如时钟抖动、量化器失配、采样噪声、开关非线性电阻以及运放参数(色化噪声、饱和电压、增益带宽、摆率等).     

用于硅像素探测器读出系统的流水线ADC设计

设计了一款用于硅像素探测器读出系统的13 bit、20 MS/s流水线ADC芯片.该芯片的核心模块主要包括乘法数模单元(MDAC)、全差分跨导运算放大器(OTA)、动态锁存器、双相非交叠时钟产生电路等,并采用130 nm CMOS商业标准工艺完成了电路设计与仿真.后仿真结果表明,该ADC性能指标满足项目需求:工作电压为...     

A baseband processor for impulse ultra-wideband communications

This paper presents a baseband processor architecture for pulsed ultra-wideband signals. It consists of an analog-to-digital converter (ADC), a clock generation system, and a digital back-end. The clock generation system provides different phases of a 300-MHz clock using four differential inverter stages. The specification of the jitter standard deviation is 100 ps. The Flash interleaved ADC provides four bit samples at 1.2 Gsps. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 65 /spl mu/s. The entire synchronization algorithm is implemented in the digital domain, without feeding any signals back to the clock control. The baseband processor and ADC were implemented on the same 0.18-/spl mu/m CMOS die at 1.8 V as part of a complete baseband transceiver. A wireless data rate of 193 kb/s is demonstrated.     

A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators

In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved oversampled ADC is introduced. Unlike previous delta–sigma bandpass ADCs that require accurate digital-to-analog converters and high-speed analog circuits, the proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition, as well as in nonideal condition, in the presence of nonlinearity, sampling clock jitter, and mismatch.      

基于频谱平均法的ADC模块性能评估

采用频谱平均法分析时钟抖动和加性白噪声对ADC(A/D转换器)模块噪声基底的影响,推导出噪声基底的数学公式,并通过仿真验证了其正确性。结合公式,改变信号频率或采样频率进行采样,绘出相应的噪声基底频谱,观测噪声基底的变化,可以推断出时钟抖动和加性白噪声的影响,借此评价采样保持电路和外围电路的性能,决定是否要对其进行改进。仿真分析表明,这是一种评估ADC系统性能的好方法,为其改进提供了理论支持。     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.     

Relationship between ADC performance and requirements of digital-IF receiver for WCDMA base-station

The recent rapid development of digital wireless systems has led to the need for multistandard, multichannel radiofrequency (RF) transceivers. The paper presents the relationship between the performance of a bandpass-sampling analog-to-digital converter (ADC) and the requirements of a digital intermediate-frequency receiver for a wideband code-division multiple-access (WCDMA) base-station. As such, the ADC signal-to-noise ratio (SNR), the derivation of the receiver sensitivity using the SNR/spurious free dynamic range (SFDR) of the ADC, the effect of the ADC clock jitter and receiver linearity, plus the relationship between the receiver IF and the ADC sampling frequency are all analyzed. As a result, when a WCDMA base-station receiver has a data rate of 12.2 kbps, bit error rate (BER) of 0.001, and channel index, k, of 5 (sampling frequency of 122.88 MHz and IF of 92.16 MHz), the performance of a bandpass-sampling ADC was analytically determined to require a resolution of 14 bits or more, SNR of 66.6 dB or more, SFDR of 86.5 dBc or more, and total jitter of 0.2 ps or less, including internal ADC jitters and clock jitters.     

关于ADC测试平台的探讨

介绍了ADC动态指标测试的常用方法和测试平台的基本组成,着重分析了对ADC性能测试时,输入采样时钟抖动对ADC动态性能的影响。同时还对测试信号频率和幅度的选择以及供电电源的指标与ADC动态的关系进行了详细分析。ADC测试平台的研究,对于ADC板卡设计及动态性能测试有一定的指导意义。     

Current-mode cyclic ADC for low power and high speed applications

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements.<>     

开关变换器补偿网络的频域设计与仿真

文章主要讨论在频域下对变换器补偿网络的设计问题,为非理想Buck电路设计了电压型补偿网络,并通过MATLAB软件对开关变换器系统的开环传递函数进行了分析,并用simulink搭建了电路模型,比较了在开环和闭环两种情况下负载和输入电压扰动时输出电压的波形,得出了较为理想的结果,给变换器的环路设计提供了参考。     

A 63 dB SNR, 75-mW Bandpass RF Σ∆ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-μm SiGe BiCMOS Technology

A fourth-order continuous-time LC bandpass sigma-delta ADC is designed using a new architecture with only non-return-to-zero feedback DACs to mitigate problems associated with clock jitter, along with individual control of coefficients in the noise transfer function. The ADC performs direct digitization of RF signals around 950-MHz center frequency with a 3.8-GHz clock. The operation of the proposed ADC architecture is examined in detail and extra design parameters are introduced to enhance the operating range and improve the stability of the ADC. Measurement results of the ADC, implemented in IBM 0.25-mum SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz, while consuming 75 mW of power from plusmn1.25-V supply