一种用于片上网络的拥塞感知哈密尔顿最短路径路由算法

类脑处理器能够支持多种脉冲神经网络SNN的部署来完成多种任务。片上网络NoC能够用较少的资源和功耗解决片上复杂的互连通信问题。现有的类脑处理器多采用片上网络来连接多个神经元核,以支持神经元之间的通信。SNN在时间步内瞬时突发的通信会在短时间内产生大量的脉冲报文。在这种通信行为下,片上网络会在短时间内达到饱和,造成网络拥塞。片上网络中非拥塞感知路由算法会进一步加剧网络拥塞状态,如何在每一个时间步内有效处理这些数据包,从而降低网络延迟,提高吞吐率,成为了目前需要解决的问题。首先对SNN的瞬时猝发通信特性进行了分析;然后提出一种拥塞感知的哈密尔顿路径路由算法,以降低NoC平均延迟和提高吞吐率;最后,使用Verilog HDL实现该路由算法,并通过模拟仿真进行性能评估。在网络规模为16×16的2D Mesh结构的片上网络中,相对于没有拥塞感知的路由算法,在数量猝发模式和概率猝发模式下,所提出的拥塞感知路由算法的NoC平均延迟分别降低了13.9%和15.9%;吞吐率分别提高了21.6%和16.8%。     

NoC在纳米计算结构下的延迟与拥塞优化映射

片上网络(NoC)映射的性能严重依赖于该网络拥有的互联结构.在自组装的纳米计算结构上探索了NoC映射问题,特别研究了在该结构上与最小延迟与拥塞相关的映射问题.提出了一个用于评估传输延迟的模型,并提出了SWMAP映射算法,使应用任务能够映射到具有小世界特性的纳米计算结构上.该算法使用了两种应用任务测试样例进行测试,实验结...     

一种改进的基于延迟的TCP拥塞避免算法

基于延迟的TCP拥塞避免算法（DCA）提高了系统的吞吐量,但在某些情况DCA表现出较差的性能。通过对RTT的分析发现,变化的传输延迟和延迟ACK将对使用RTT指示拥塞引入明显误差,从而影响DCA算法的准确性。为此提出了一种改进的DCA算法,在判断网络是否拥塞时,先消除这些明显误差。仿真试验表明,该算法更加准确地监测到网络拥塞,改进了TCP性能,提高网络的吞吐量。     

一个适用于DTN网络的拥塞避免与解除方案

DTN(delay-tolerant network,延迟容忍网络)的网络特点及其采用的托管传输机制易造成网络受限资源(如缓存、带宽等)的耗尽,形成网络拥塞,导致网络性能的下降。传统TCP拥塞控制机制不适用于DTN网络。提出了一个全新的适用于DTN网络的拥塞避免与拥塞解除方案。拥塞避免根据在足够小的时间段内DTN链路的传输延迟和传输能力的确定性,建立DTN网络有向多径图,对数据发送速率、接收速率、带宽使用等链路负载分割与约束控制,尽可能地提高网络资源的利用率。拥塞解除在节点存储资源划分的基础上,通过节点内存储资源转换与节点间报文转移相结合的方法,解除DTN网络的拥塞状况。仿真结果显示,与其他DTN拥塞控制机制相比,所提方案具有良好的报文交付率、网络开销等网络性能。     

网络中的拥塞避免控制模型的仿真分析

研究延迟网络中的拥塞避免控制方法.在延迟网络中,随机分配网络资源,造成延迟网络资源的局限性较强,容易造成延迟网络拥塞.传统的拥塞避免控制方法是根据网络链路的反馈回执进行拥塞控制的,但是由于延迟网络的链路均匀性较差,无法建立准确的拥塞反馈回执,造成拥塞避免控制的效果较差.为了避免上述缺陷,提出了一种加权排队控制算法的延迟网络拥塞避免控制模型.对延迟网络参数进行训练,计算延迟网络的带宽,从而为延迟网络的拥塞避免控制提供准确的数据基础.建立加权排队控制模型,能够实现延迟网络的拥塞避免控制.实验结果表明,利用改进算法进行延迟拥塞避免控制,能够有效提高延迟网络的数据传递效率.     

改进TCP拥塞控制算法的仿真及应用研究

研究网络拥塞优化控制问题.由于网络承载量猛增,产生堵塞,延迟增加,使网络效率降低.传统网络的TCP拥塞控制算法不能区分网络拥塞和网络随机错误丢包,导致网络带宽利用率低,网络拥塞严重,甚至导致网络崩溃.为了降低网络拥塞的概率,提出了一种改进的TCP拥塞控制算法.改进的网络拥塞控制算法首先通过对网络状态进行预测,能够有效区分网络拥塞和网络随机错误丢包,同时对TCP网络拥塞控制算法的拥塞避免、快速重传和快速恢复机制进行改进,改善网络性能.最后采用NS2仿真器对算法进行仿真,实验结果表明,提高了网络平均吞吐量,带宽利用率更高,很好的避免了网络拥塞.     

基于网络包延迟偏差的硬件动态拥塞控制机制

互连网络已经成为提升高性能计算系统性能的技术瓶颈。对高性能互连网络中的拥塞控制进行研究,针对通信热点的形成过程,给出了一种基于网络包延迟偏差的硬件动态拥塞控制机制CMDPD,利用网络包传输延迟偏差预判网络拥塞状态,控制端到端网络注入,避免拥塞形成。构建了模拟环境,在Fat-tree和Dragonfly两种网络结构下,对CMDPD进行了模拟实验。结果表明,在Fat-tree网络中CMDPD的吞吐率可提高5%~12%。     

基于改进BBR的数据报拥塞控制协议

数据报拥塞控制协议(Datagram Congestion Control Protocol,DCCP)是提供拥塞控制和不可靠传输特点的实时多媒体基础协议,DCCP中的CCID2算法仍然采用AIMD的控制机制,这种传统的Loss-Base拥塞控制模型已经不适用于目前高BDP的网络环境,容易引起缓冲区膨胀现象,导致网络延迟增加和抖动等问题.与Loss-Base的算法相比,BBR算法可以有效地控制网络延时,最大限度避免网络排队的情况,在丢包率较高的情况下仍可以保持一定的带宽利用率和较低的链路延时,因此适合于DCCP实时流媒体的应用的协议.本文在DCCP中引入了BBR算法并做相应的改进,增加了丢包率检测模型,使用延时与带宽积模型的拥塞控制算法对上述问题进行改进.通过模拟实验证明,本方法在高负载情况下连接的平均延迟相比CCID2降低了20%,在丢包率较高的环境下也能保持良好的吞吐量.     

网络拥塞控制模型Hopf分岔的PD控制

网络拥塞会导致信息丢失,时延增加,甚至系统崩溃。由于无线接入网络中的时变衰落和分组错误率,使得TCP协议在网络拥塞控制更加复杂。TCP Westwood是专门为高速无线网络设计的,大大提高了网络带宽的利用率,改善了网络性能。TCP Westwood/AQM拥塞控制的连续流体流模型被引用,源端采用TCP Westwood拥塞控制协议,路由器端采用主动队列管理(AQM)机制中的随机早期检测(RED)算法。为了延迟无线接入网络拥塞控制模型中霍普夫(Hopf)分岔现象的发生,采用比例微分(PD)控制器,通过选择通信延迟作为分岔参数,分析无线网络系统中的Hopf分岔行为,并由理论分析得知当分岔参数超过临界值时系统发生Hopf分岔。利用中心流形和规范型理论,推导得出系统发生Hopf分岔的条件和反映Hopf分岔性质,方向和周期的参数,数值仿真验证理论分析的准确性,表明PD控制器的有效性。     

ACK报文拥塞对网络性能影响的研究

为了提高网络性能和安全、设计更有效地队列拥塞控制算法,通过研究现有的一些主动队列拥塞控制算法发现:大多数的拥塞控制算法的实现是基于队列长度或平均队列长度,这使得算法在提高网络整体性能上具有局限性。本文在现有的网络队列拥塞控制算法的基础上,将ACK信息确认报文传输状态引入到队列拥塞控制算法研究的系统中,通过仿真实验发现:ACK数据报文的传输状态在很大程度上影响着网络的吞吐量、数据包的传输延迟等。     

基于拥塞控制的片上网络多播路由算法

为了满足片上网络日益丰富的应用要求,多播路由机制被应用到片上网络,以弥补传统单播通信方式的不足。以Mesh和Torus类的片上网络为例,分析了基于路径的3种多播路由算法(即XY路由、UpDown路由和SubPartition路由算法),并研究了相应的拥塞控制策略。通过模拟实验表明,多播较单播通信具有更小的平均传输延时和更高的网络吞吐量,且负载分配均匀;特别是SubPartition路由算法随着规模增大效果更加明显;提出的多播拥塞控制机制,能更有效地利用多播通信,提高片上网络的性能。     

一种动态分配虚拟输出队列结构的片上路由器

传统虚通道流控技术的片上路由器通过增加虚通道缓解排头阻塞引起的链路吞吐率下降以及网络拥塞的同时,面临缓冲区低利用率、仲裁开销较大等问题.而动态虚通道流控的片上路由器虽可通过动态管理缓冲单元,提高缓冲区利用率与链路吞吐率,但却不可避免流控与仲裁逻辑复杂度与开销的快速增长.为了提高链路吞吐率与缓冲区利用率,获得较好的性能与开销折中,提出一种动态分配虚拟输出队列结构的片上路由器DAVOQ,该结构通过快速链表动态组织虚拟输出队列,同时使用超前路由机制以简化仲裁逻辑,优化流水线.模拟与综合的结果表明,相比传统虚通道路由器,DAVOQ路由器改善报文传输延迟与吞吐率的同时,在0.13μm CMOS工艺下,节省了15.1%的标准单元面积与12.9%的漏电流功耗;而相比动态虚通道路由器,DAVOQ路由器能够以较小的吞吐率损失获得可观的延迟改善,同时节约15.6%的标准单元面积与20.5%的漏电流功耗.     

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

This paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms.     

CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era

In order to fulfill the ever-increasing demand for high-speed and high-bandwidth, wireless-based MCSoC is presented based on a NoC communication infrastructure. Inspiring the separation between the communication and the computation demands as well as providing the flexible topology configurations, makes wireless-based NoC a promising future MCSoC architecture. However, congestion occurrence in wireless routers reduces the benefit of high-speed wireless links and significantly increases the network latency. Therefore, in this paper, a congestion-aware platform, named CAP-W, is introduced for wireless-based NoC in order to reduce congestion in the network and especially over wireless routers. The triple-layer platform of CAP-W is composed of mapping, migration, and routing layers. In order to minimize the congestion probability, the mapping layer is responsible for selecting the suitable free core as the first candidate, finding the suitable first task to be mapped onto the selected core, and allocating other tasks with respect to contiguity. Considering dynamic variation of application behaviors, the migration layer modifies the primary task mapping to improve congestion situation. Furthermore, the routing layer balances utilization of wired and wireless networks by separating short-distance and long-distance communications. Experimental results show meaningful gain in congestion control of wireless-based NoC compared to state-of-the-art works.     

A novel heterogeneous congestion criterion for mesh-based networks-on-chip

In recent years, congestion in Networks-on-chip (NoC) has emerged as an important research topic due to the increasing number of processing cores. To solve the congestion, all the methods that have been proposed require a congestion criterion to detect whether a node is congested or not. All the congestion criteria that have been developed so far have similar behavior for all nodes in the network. In this paper, for the first time, a heterogeneous congestion criterion is proposed for a two-dimensional mesh network that is determined for each node based on its betweenness centrality. This criterion can be generalized to the other topology such as torus easily. This criterion is calculated before the network starts up and does not have any overhead in run time. Using this criterion will reduce the average latency of any congestion-aware method, such as congestion-aware routing algorithms. The evaluation section shows that the use of this criterion in three famous routing algorithms reduces the average latency up to 48% (21% on average for all algorithms and traffic patterns) in both real and synthetic traffics. In addition, the usage of this criterion reduces the power consumption in all simulation conditions because of reducing the average latency and lack of overhead. It is also shown at the end of the evaluation section that an increase in the network size will result in better performance of this criterion.     

Arbiter synthesis approach for SoC multi-processor systems

The increasing complexity of Multi-Processor System on Chip (MPSoC) is requiring communication infrastructures that will efficiently accommodate the communication needs of the integrated computation resources. Exploring the arbitration space is crucial for achieving low latency communication. This paper illustrates an arbiter synthesis approach that allows a high performance MPSoC communication for multi-bus and Network on Chip (NoC) architectures. A cost function has been formulated in order to affect the priority order to each component or each set of components in a manner that minimizes the communication latency and generates a multi-level arbiter. The performance of the proposed approach have been analyzed in a design of an 8 × 8 ATM switch subsystem and a MPEG4 decoder mapped onto a 2-D mesh NoC. The results demonstrate that the MPSoC arbiter is well suited to provide high priority communication traffic with low latencies by allowing a preemption of lower priority transport. The sum of the mean waiting time at the eight ports of the ATM switch is minimum under the MPSoC arbitration scheme (4.30 cycle per word) while it is 3.00 times larger under the poorer performance arbitration scheme. In the case of the MPEG4 decoder, the average packet latency of the MPSoC is about 480 cycles while it is 640 cycles in the poorer performance arbitration scheme under a 0.4 flits/cycle injection rate.     

拥塞窗口自适应的TCP拥塞避免算法

针对TCP Reno拥塞避免阶段拥塞窗口增长不够平滑的缺陷,在研究分析TCP Reno拥塞控制算法的基础上,提出一种基于拥塞窗口自适应调整增长因子的拥塞避免新算法——在拥塞避免阶段采用压缩特性的对数增长因子函数。在网络情况良好阶段,该因子增长速率大,以充分利用网络资源;而在逼近网络拥塞阶段,该因子以较小的速率增长,以避免过激的拥塞丢包。数学分析说明了新算法的可行性,并通过NS仿真对其吞吐量、公平性、友好性进行评估。仿真结果表明该改进的TCP拥塞避免算法的有效性。     

一种考虑节点拥塞情况的DTN概率路由算法*

容迟网络是一种新型网络,其概率路由算法根据历史相遇频率对相遇概率进行计算与更新,通过相遇概率判断是否转发报文。当节点缓存受限时,在网络中采用概率路由算法使得节点很容易发生拥塞,对报文的传送产生影响。为了减小拥塞对概率路由算法的影响,提出了一种考虑节点拥塞情况的概率路由算法,将节点相遇的概率和节点拥塞的情况综合起来,得到一个报文的递交概率,降低了由于拥塞对网络性能的影响,提高了报文的递交率,减小了报文在缓存中排队等候的时间。仿真结果表明,与传统的概率路由算法相比,在改进后的概率路由算法中报文递交率显著提高,平均延迟也在降低。