Performance analysis of a land mobile satellite system using importance sampling

Land mobile communication using satellites has become widespread. However, estimation of its average bit-error rate is still challenging due to the complexity of various system components, such as the nonlinearity of traveling wave tube amplifiers (TWTAs), intersymbol interference, spread spectrum under fading, or jamming conditions. The analytical approach using closed form solutions is very difficult if not impossible. Monte Carlo (MC) simulation can offer an alternative method of performance estimation; however, the use of MC simulation is often limited by an excessive computational burden. Importance sampling (IS) is an efficient simulation method that can greatly reduce this computational overhead although it requires additional modeling and a careful biasing scheme. We propose an integrated IS model which combines error event simulation, a conditional IS method, and an asymptotically efficient method for the effective estimation of the error rate. Simulation results conditioned on different channel parameters such as the backoff of a TWTA, jamming signal strength, and elevation angle of the low-Earth orbit satellite are provided. Comparisons between the proposed method and the MC method show that a great reduction in simulation time, as well as increased accuracy, can be achieved with the IS method.     

触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.     

Dual-frequency braking in AC drives

Many variable frequency drive (VFD) applications require infrequent or partial braking. The use of a regenerative circuit, or of a dynamic braking resistor, adds significant cost to the VFD. This paper presents a method to obtain braking torque in nonregenerative AC drives without the need for additional power circuits. With this method, braking energy is absorbed from the rotating inertia at the applied frequency and is dissipated in the motor at a second loss-inducing frequency. Theoretical results that illustrate the usefulness and limitations of the proposed approach are given. Test results with low-voltage and medium-voltage drives are included in this paper. As compared to DC injection braking, the proposed method allows continuous estimation of motor speed and gives much higher braking torque per ampere.     

基于MC74型电路的无线数字温度传感器

MC74型串行数字温度传感器具有价格低、精度高、串行线性输出等优点.介绍该电路的主要工作特性及工作原理,给出利用MC74设计的无线数字温度传感器电路的原理及部分程序代码.     

A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits

Nano-scale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. On the other hand, the impacts of process variations on characteristics of the circuits in nano era make statistical approaches as an unavoidable option for soft error rate estimation procedure. In this paper, we present a novel statistical Soft Error Rate estimation framework. The vulnerability of the circuits to soft errors is analyzed using a newly defined concept called Statistical Vulnerability Window (SVW). SVW is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the given circuit. The SER is calculated using a probabilistic formulation based on the parameters of SVWs. Experimental results show that the proposed method provides considerable speedup (about 5 orders of magnitude) with less than 5 % accuracy loss when compared to Monte-Carlo SPICE simulations. In addition, the proposed framework, keeps its efficiency when considering a full spectrum charge collections (more than 36X speedups compared to the most recently published similar work).     

Computationally efficient large-change statistical analysis of linear electronic circuits

A new method is presented for efficient statistical analysis of linear electronic circuits, when small and large parameter tolerances are given. The statistically generated value of the parameter is considered as a faulted value, as it deviates from the nominal thus enabling the application of a simulation method which uses a new approach of concurrent fault simulation. This method adds new elements to the circuit, representing individual parameter increments, while keeping the topology of the original one. The equations for the original and several perturbed circuits are formulated and solved simultaneously. In this way, redundant computations are avoided in both the equation formulation and equation solving phases, which shorten the simulation time. A statistical frequency and time domain tolerance simulator of linear circuits was developed on the basis of this method with effective user-friendly interface. The method is especially suited for yield sensitivity to some selected circuit parameters estimation. Here simulation results of several benchmark circuits are presented. Efficiency analysis is also included.     

基于翻转信息熵的组合逻辑电路功耗分析

基于信息熵的复杂度分析方法是在VLSI设计流程的高层次抽象阶段对组合逻辑电路功耗和面积进行分析估计的可行方法之一.本文通过提出新的利用翻转信息熵进行电路实现面积和功耗估计的理论方法,改善了面积和功耗估计精度.大量基于随机电路和BENCHMARK电路的实验结果表明,上述方法能够使面积和功耗估计的相对误差分别降低24.3% (从12.74%到9.65%)和15.4% (从13.67%到11.57%).     

MC V-BLAST系统的MIMO信道盲估计

本文研究多载波垂直分层空时(MC V-BLAST)系统的下行频率选择性衰落多输入多输出(MIMO)无线信道估计问题.本文首先为MC V-BLAST系统提出了一种新颖的移不变性编码方法.利用上述移不变性性质,本文进一步提出了相应的下行频率选择性衰落MIMO无线信道的盲估计方法.仿真结果表明了本文移不变性编码方法的有效性和信道盲估计方法的性能.     

基于Copula理论的芯片多元参数成品率估算方法

当前芯片参数成品率研究主要局限于单一性能指标成品率估算或对多个单性能指标成品率进行均衡优化.针对此类方法易造成参数成品率缺失的问题,本文提出一种基于Copula理论的芯片多元参数成品率估算方法.该方法首先针对漏电功耗及芯片时延性能指标,构建具有随机相关性的漏电功耗及芯片时延模型;然后利用鞍点线抽样方法对漏电功耗及芯片时延的边缘分布概率进行求解;最后根据Copula理论得到准确的芯片多元参数成品率估算结果.仿真结果表明,相较于蒙特卡罗仿真,本文方法具有较高的仿真效率,仿真时间减少了12%以上,而且在不同国际电路与系统研讨会（International Symposium on Circuits and Systems,ISCAS）基准电路下,该方法与蒙特卡罗仿真结果的相对误差均保持在9%以内,能够在任意性能指标约束下,对芯片多元参数成品率进行有效估算,可为芯片设计人员提供同时考虑多个性能指标的参数成品率信息.     

Least-square estimation of average power in digital CMOS circuits

The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this work, two algorithms based on least square estimation are proposed for determining the average power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits. Least square estimation converges faster by attempting to minimize the mean square error value during each iteration. Two statistical approaches namely, the sequential least square (SLS) estimation and the recursive least square estimation are investigated. The proposed methods are distribution independent in terms of the input samples, unbiased and point estimation based. Experimental results presented for the MCNC'91 and the ISCAS'89 benchmark circuits show that the least square estimation algorithms converge faster than other statistical techniques such as the Monte Carlo method and the DIPE     

考虑时间因素的不同基本门故障概率计算

在门级电路的可靠性概率评估方法中,基本门的故障概率p一般人为设定或以常数形式出现.考虑到不同基本门的故障概率具有随时间变化的特性并结合其输入导线,本文构建了考虑输入负载的随时间变化的不同基本门的故障概率模型.理论分析与实验结果表明,基于弱链接模型的双峰对数正态分布更适合用来表示输入导线故障概率的时间分布.用本文方法、美国军用标准MIK-HDBK-217及Monte Carlo方法计算了ISCAS85基准电路的可靠度并进行了比较,还通过了行业标准的检验,结果验证了本文所构建模型的合理性.     

基于概率表达式的MPRM电路功耗计算方法

采用基于信号概率的功耗计算模型进行MPRM（Mixed Polarity Reed-Muller）电路功耗优化,信号概率计算是功耗计算的关键.提出一种基于概率表达式的MPRM电路功耗计算方法.该方法兼顾信号概率计算的时间效率和准确性,对MPRM电路中不存在空间相关性的信号通过在电路中传播信号概率的方式计算其信号概率,存在空间相关性的信号则利用概率表达式计算其信号概率,并在电路中传播概率表达式以解决空间相关性问题,在此基础之上根据基于信号概率建立的解析动态功耗和静态功耗计算模型计算电路功耗.为进一步提高时间效率,该方法采用二元矩图表示概率表达式.使用基准电路对所提出方法进行了验证,并与其他采用不同信号概率计算方法的MPRM电路功耗计算方法进行了比较.结果表明所提出方法准确有效.     

Petri net modeling of gate and interconnect delays for power estimation

Switching activity estimation is an important step in average power estimation of VLSI circuits at the gate level. In this paper, we present a novel approach based on Petri net modeling for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. We propose a new type of Petri net called hierarchical colored hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity. The logic circuit is first modeled as a gate signal graph (GSG) which is then converted into the corresponding HCHPN and simulated as a Petri net to obtain the switching activity estimates and the power values. The proposed method is accurate and fast compared to other simulative methods. Experimental results are provided for ISCAS '85 and ISCAS '89 benchmark circuits and compared with the commercial tools, PowerMill, and Prime Power.     

Generation of Generalized Impedance Converter Circuits Using NAM Expansion

The generation of the voltage generalized impedance converter (VGIC) circuits using a nodal admittance matrix (NAM) expansion is given in detail. Thirty-two equivalent circuits using current conveyors (CCII) or inverting current conveyors (ICCII) or a combination of both are generated. The reported circuits are suitable for realizing inductors or frequency dependent negative resistors (FDNR) using grounded passive elements. Similarly the generation of the current generalized impedance converter (CGIC) circuits published recently is reexamined and this resulted in 16 more new CGIC circuits using an alternative NAM expansion. Modification of two of the generated circuits to realize a floating inductor or floating FDNR is also given together with Spice simulation results.     

采用MC34262的功率因数校正电路研制

分析了开关电源、变频调速等电路功率因率低、谐波分量大的原因，提出了有源功率因素校正（PFC）技术的解决方案；并详细介绍了专用源功率因素控制集成电路MC34262的内部框图的功能；给出了采用MC34262研制的有源PFC电路的详细电路和参数，并详细分析了工作原理。     

Deinterlacing using variational methods

We present a variational framework for deinterlacing that was originally used for inpainting and subsequently redeveloped for deinterlacing. From the framework, we derive a motion adaptive (MA) deinterlacer and a motion compensated (MC) deinterlacer and test them together with a selection of known deinterlacers. To illustrate the need for MC deinterlacing, the problem of details in motion (DIM) is introduced. It cannot be solved by MA deinterlacers or any simpler deinterlacers but only by MC deinterlacers. The major problem in MC deinterlacing is computing reliable optical flow [motion estimation (ME)] in interlaced video. We discuss a number of strategies for computing optical flows on interlaced video hoping to shed some light on this problem. We produce results on challenging real world video data with our variational MC deinterlacer that in most cases are indistinguishable from the ground truth.     

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13-/spl mu/m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.     

Power estimation methods for sequential logic circuits

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2^N where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies     

基于弹性网稀疏表示的芯片参数成品率估算方法

当前集成电路芯片参数成品率估算通常预设大量扰动基函数进行芯片性能模型构建,易造成成品率估算方法复杂度过高.而若随意减少扰动基函数数量,则极易造成成品率估算精度缺失.针对此问题,本文提出一种芯片参数成品率稀疏估算方法.该方法首先根据工艺参数扰动建立具有随机不确定性的漏电功耗模型;然后按照关键度高低,利用弹性网自适应选取关键扰动基函数对漏电功耗模型进行稀疏表示建模;最后,利用贝叶斯理论及马尔科夫链方法对漏电功耗成品率进行估算.实验结果表明,该方法不仅可以使所构建的漏电功耗模型具有一般性和稀疏性优点,而且能够对漏电功耗成品率进行准确估算,与蒙特卡罗仿真结果相比估算误差不超过5%.同时,相较于蒙特卡罗采样,该方法还可以大幅减少算法仿真时间,具有更好的仿真效率.