隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.     

隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.     

非对称HALO结构的全耗尽SOI二维阈值电压解析模型

在考虑了隐埋层与硅层的二维效应的基础上提出非对称HALO结构的全耗尽SOI二维阈值电压解析模型,该模型计算了在不同硅膜厚度,掺杂浓度,HALO区占沟道比例的条件下的阈值电压.模型结果与二维数值模拟软件MEDICI的模拟结果较好的吻合,该模型对HALO结构的物理特性和工艺设计有很好的指导意义.     

全耗尽型浮空埋层LDMOS的耐压特性

提出了一种新的全耗尽型浮空埋层LDMOS(FB-LDMOS)结构.全耗尽n型埋层在器件的体内产生新的电场,该电场调制了漂移区电场,使得在降低漂移区漏端电场的同时提高了源侧和中部电场REBULF效应.分析了埋层的浓度、厚度、长度等对器件击穿电压的影响.借助二维仿真软件MEDICI,该新结构的击穿电压由传统LDMOS的585.8V提高到886.9V,提高了51.4%.     

全耗尽型浮空埋层LDMOS的耐压特性

提出了一种新的全耗尽型浮空埋层LDMOS(FB-LDMOS)结构.全耗尽n型埋层在器件的体内产生新的电场,该电场调制了漂移区电场,使得在降低漂移区漏端电场的同时提高了源侧和中部电场REBULF效应.分析了埋层的浓度、厚度、长度等对器件击穿电压的影响.借助二维仿真软件MEDICI,该新结构的击穿电压由传统LDMOS的585.8V提高到886.9V,提高了51.4%.     

复合介质层SOI高压器件电场分布解析模型

提出复合介质埋层SOI(compound dielectric buried layer SOI,CDL SOI)高压器件新结构,建立其电场和电势分布的二维解析模型,给出CDL SOI和均匀介质埋层SOI器件的RESURF条件统一判据.CDL SOI结构利用漏端低k(介电常数)介质增强埋层纵向电场,具有不同k值的复合介质埋层调制漂移区电场,二者均使耐压提高.借助解析模型和二维数值仿真对其电场和电势进行分析,二者吻合较好.结果表明,对低k值为2的CDL SOILDMOS,其埋层电场和器件耐压分别比常规SOI结构提高了82%和58%.     

复合介质层SOI高压器件电场分布解析模型

提出复合介质埋层SOI(compound dielectric buried layer SOI,CDL SOI)高压器件新结构,建立其电场和电势分布的二维解析模型,给出CDL SOI和均匀介质埋层SOI器件的RESURF条件统一判据.CDL SOI结构利用漏端低k(介电常数)介质增强埋层纵向电场,具有不同k值的复合介质埋层调制漂移区电场,二者均使耐压提高.借助解析模型和二维数值仿真对其电场和电势进行分析,二者吻合较好.结果表明,对低k值为2的CDL SOILDMOS,其埋层电场和器件耐压分别比常规SOI结构提高了82%和58%.     

OISD MOSFET阈值电压建模与结构设计

对一种新型半绝缘SOI MOS器件的阈值电压进行建模,该器件采用源漏注氧OISD技术,具有优良的自加热效应抑制能力和耐压特性.由于沟道中存在复杂的二维势场分布,OISD MOSFET阈值电压,亚阈值斜率及短沟道效应均受到硅窗口尺寸的调制.给出了一个基于数值仿真的OISD MOSFET阈值电压简单模型,该模型可指导器件结构设计,并通过MEDICI二维数值仿真进行验证.最后,对OISD MOSFET亚阈值斜率、短沟道阈值电压偏移以及DIBL因子等重要电学参量进行详细的研究.     

短沟Trench MOSFET阈值电压解析模型

传统MOS器件的阈值电压模型被广泛地用于分析Trench MOSFET的阈值电压,这种模型对于长沟道和均匀分布衬底的MOS器件来说很合适.但是对于Trench MOSFET器件来说却显现出越来越多的问题,这是因为Trench MOSFET的沟道方向是垂直的,其杂质分布也是非均匀的.本文基于二维电荷共享模型,给出了Trench MOSFET的一种新的阈值电压解析模型,该模型反映了器件的阈值电压随不同结构和工艺参数变化的规律,模型的结果和器件仿真软件Sivaco TCAD的仿真结果吻合较好.该模型较好地解决了以往所用的Trench MOSFET阈值电压模型计算不准确的问题.     

具有埋层的大功率集成器件二维简化模型分析

对具有埋层结构的集成大功率器件提出了导通电阻自限制二维模型.在假定条件成立时,推导出器件二维模型导通电阻自限制公式,得出了具有埋层结构的集成大功率器件结构其比导通电阻是随着面积不断增大的结论.通过实验,证实了该结论预测趋势的正确性.该结论对类似集成化大功率器件结构设计具有一定的指导作用.     

A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect

In this paper, we propose a unique feature exhibited by novel nanoscale metal oxide semiconductor field effect transistors (MOSFETs) with an undoped buried region (UBR) under the channel and a buried oxide only under the source and drain region. The key idea in this work is suppression of the self-heating effect and gate–substrate capacitance improvement by modifying the buried layer. As a result, we demonstrate that the proposed structure called undoped buried region MOSFET (UBR-MOSFET) exhibits gate–substrate improvement in addition to excellent temperature performance when compared to conventional structures. Using two-dimensional and two-carrier device simulation, we have examined various design issues of the UBR-MOSFET and provided the reasons for the improved performance. The simulated results show that the novel structure is a suitable device for high temperature and electrical performances.     

A new structure and its analytical breakdown model of high voltage SOI device with Step Unmovable Surface Charges of buried oxide layer

A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.     

一种具有部分高k介质埋层的SOI场pLDMOS器件

提出了一种具有部分高k介质埋层的SOI场pLDMOS器件。将传统结构的部分埋氧层替换为介电常数更高的Si₃N₄,降低了漂移区的积累层电阻,使器件获得更低的比导通电阻,同时减弱了自热效应。与传统结构进行仿真对比,发现新结构基本保持了与传统结构相当的击穿电压,但比导通电阻降低了24%,最高温度降低了59%。     

A novel nanoscale SOI MOSFET with Si embedded layer as an effective heat sink

A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications.     

700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

A study on channel design for 0.1 μm buried p-channel MOSFETs

This paper investigates the channel design for buried p-channel MOSFETs with an effective channel length of 0.1 μm via simulations using the two-dimensional device simulator PISCES IIB. A new three-layer design is considered with the objective of obtaining low junction capacitance while maintaining high current drive and suppressing punchthrough. The channel design consists of a p-type layer under the gate oxide, an n-type anti-punchthrough layer below the p-type layer followed the substrate with a doping concentration of 1e17/cm³. By optimizing the doping structure, an attempt is made to investigate fundamental limits of the buried channel design. In concurrence with published results, it is shown that there is a maximum allowable thickness for the first layer, while the thickness of the anti-punchthrough layer has a minimum value in order to effectively suppress punchthrough. The above constraints enable devices with good subthreshold characteristics (subthreshold swing <90 mV/Dec) as well as high transconductance which is a matter of concern for ultra-thin buried layers. While simulation results show that it is possible to fabricate buried p-channel MOSFETs with n-type polysilicon gate electrodes in the 0.1 μm regime, it is also evident that advanced doping and low temperature fabrication technologies are needed that provide control over doped layers of ultra-thin dimensions     

薄硅层阶梯埋氧PSOI高压器件新结构

基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与相关结构参数的关系,在埋氧层为2μm,耐压层为0.5μm时,其埋氧层电场提高到常规结构的1.5倍,击穿电压提高53.5%。同时,由于源极下硅窗口缓解SOI器件自热效应,使得在栅电压15V,漏电压30V时器件表面最高温度较常规SOI降低了34.76K。     

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of E_I > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices.     

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device V_th is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.     

以Si3N4为埋层的SOI结构制备与器件模拟

为了减少经典SOI器件的自加热效应,首次成功地用外延方法制备以Si3N4薄膜为埋层的新结构SOSN,用HRTEM和SRP表征了SOI的新结构.实验结果显示,Si3N4层为非晶状态,新结构的SOSN具有良好的结构和电学性能.对传统SOI和新结构SOI的MOSFETs输出电流的输出特性和温度分布用TCAD仿真软件进行了模拟.模拟结果表明,新结构SOSN的MOSFET器件沟道温度和NDR效益都得到很大的降低,表明SOSN能够有效地克服自加热效应和提高MOSFET漏电流.