共查询到20条相似文献,搜索用时 31 毫秒
1.
Houtsma V.E. Holleman J. Salm C. Widdershoven F.P. Woerlee P.H. 《Electron Device Letters, IEEE》1999,20(7):314-316
The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si0.7 Ge0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices 相似文献
2.
Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the Ig versus Vg characteristics for the p+/pMOSFET are essentially identical to those for the n+/nMOSFET; however, when measured in inversion, the p+/pMOSFET exhibits much lower gate current for the same |Vg|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p+/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p+-polysilicon gate; and (3) conduction band electron tunneling from the p+-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p+/pMOSFET, with one of them dominating in a certain voltage range 相似文献
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Saito M. Yoshitomi T. Hara H. Ono M. Akasaka Y. Nii H. Matsuda S. Momose H.S. Katsumata Y. Ushiku Y. Iwai H. 《Electron Devices, IEEE Transactions on》1993,40(12):2264-2272
A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p+ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p+-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved 相似文献
5.
The gate tunneling leakage current in dual-gate CMOSFETs exhibits strong polarity dependence when measured in inversion, although it exhibits practically no polarity dependence when measured in accumulation. Specifically, p+-gate pMOSFET shows substantially lower tunneling current than n+-gate nMOSFET when measured in inversion. This polarity dependence arises from the difference in the supply of tunneling electrons. The polarity dependent tunneling current has a significant impact on oxide reliability measurements. For example, it gives rise to a higher Tbd value for p+/pMOSFET as compared to that for n+/nMOSFET when both are biased to inversion. Rationaless are given as to why Tbd is a better gauge than Qbd for reliability assessment, and why nMOSFET is more prone to oxide breakdown than pMOSFET under normal operating conditions 相似文献
6.
Verdonckt-Vandebroek S. Crabbe E.F. Meyerson B.S. Harame D.L. Restle P.J. Stork J.M.C. Megdanis A.C. Stanis C.L. Bright A.A. Kroesen G.M.W. Warren A.C. 《Electron Device Letters, IEEE》1991,12(8):447-449
A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n+ polysilicon gate, and p+ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm2/V-s at 300 K and 980 cm2/V-s at 82 K were achieved in functional submicrometer p-MOSFETs 相似文献
7.
Ting-Kuo Kang Ming-Jer Chen Chuan-Hsi Liu Chang Y.J. Shou-Kong Fan 《Electron Devices, IEEE Transactions on》2001,48(10):2317-2322
This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density Nt, and the trap energy level Et. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N t explicitly as a function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes τ of 4.0×10-13 s and Et of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well 相似文献
8.
Tien-Chun Yang Sachdev P. Saraswat K.C. 《Electron Devices, IEEE Transactions on》1999,46(7):1457-1463
In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide 相似文献
9.
Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented. 相似文献
10.
The bias temperature instability in surface-channel p+ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔVth,BT) is induced by negative bias temperature (BT) stress in short-channel p+ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔVth,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p+-gate. For the bias temperature instability in p+ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices 相似文献
11.
To investigate the highly boron-doped SiO2 film, p+ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n+-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO2 interface and electrons accumulate near the polysilicon/SiO2 interface in p+-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p+ gate's stress time dependence of I sub is smaller than that of the n+ gate, and the electric field near the drain in the p+ -gate PMOSFET was found to be more severe than that of the n+ -gate device. The subthreshold slope of the p+-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n+-gated device did not significantly change. The actual change of V th was larger than the value derived from Δgm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO2 film, which assumes the existence of trapped holes in the p+-gate PMOSFET, is proposed to explain these phenomena 相似文献
12.
Interface trap-enhanced gate-induced leakage current in MOSFET 总被引:1,自引:0,他引:1
Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p+-gated diode can increase by two orders of magnitude when the interface trap density is increased from 1011 to 1012 cm-2-eV-1. The fact that thermal annealing at 300°C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p+-gated diode is found to be more susceptible to this interface-trap related leakage current than the n+-device, which can be explained qualitatively by an interface-trap-assisted tunneling model 相似文献
13.
de Blauwe J. van Heudt J. Wellekens D. Groeseneken G. Maes H.E. 《Electron Devices, IEEE Transactions on》1998,45(8):1745-1750
In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO2 gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism 相似文献
14.
A new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-V characteristics. The trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons, which has been experimentally verified by applying the carrier separation technique to MOSFETs with the SILC component. The energy relaxation is treated in the new model as the change in the energy level of traps before and after the capture of electrons during two-step tunneling. It is demonstrated that this model successfully represents the experimental I-V characteristics of the SILC component and, particularly, the low apparent barrier height in the Fowler-Nordheim (FN) plot of the SILC component. The calculated low barrier height is attributed to the dominance of direct tunneling mechanism on both tunneling into traps and out of traps. The impact of the energy relaxation during tunneling, used in the present model, on the I-V characteristics is discussed in terms of the trap distribution inside the gate oxide, compared with conventional elastic tunneling model 相似文献
15.
The channel field and substrate current models developed for n-MOSFETs are applicable to p-MOSFETs. The impact ionization rate extracted for holes is found to be 8×106 exp (-3.7×106/E ), where E is the electric field. The lucky electron approach was used to model the gate current of surface-channel (SC) p-MOSFETs successfully. Device degradation in p-MOSFETs is due to trapped electrons in the oxide. p-MOSFET lifetime has good correlation with gate current in SC p-MOSFETs. The correlation is better than with substrate current. I G can be larger in a buried-channel (BC) p-MOSFET than in a comparable SC n-MOSFET. This makes the SC MOSFET a much more reliable device. Device lifetime of a p-MOSFET under pulse stress can be predicted from DC stress data for inverterlike waveforms. For other waveforms, there is an extra degradation probably caused by the excess hot carriers generated during the gate turn-off transient 相似文献
16.
A CMOS VLSI technology using p- and p+ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p - poly gate is shown to be compatible with p+ poly-gated surface-channel PMOS devices 相似文献
17.
研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。 相似文献
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It is proposed to reduce the gate current by using a dipole created by two doped planes, n++ and p++, in charge control layer, dipole heterostructure field-effect transistors (dipole HFETs) fabricated in AlGaAs/GaAs use doped p++ and n ++ planes in the charge control AlGaAs layer to form a dipole that provides a considerably larger barrier between the channel and the gate than that in conventional heterostructure FETs. This leads to a reduction of the forward-biased gate current in enhancement-mode n-channel devices, by a factor of approximately 9 at 1.2 V in the experimental devices, when compared with equivalent conventional HFETs. A much broader transconductance region, in the range of 0.5-2.5-V gate bias, a higher maximum drain current, and no negative transconductance are also observed. A comparison between the gate current-voltage characteristics of conventional and dipole HFETs for 1-μm-long and 10-μm-wide gate devices is given. The measured results clearly indicate that a dipole HFET has a much smaller gate leakage current leading to superior performance of enhancement-mode devices. The results demonstrate the effectiveness of the dipole layer concept for digital HFET devices 相似文献
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Under a static negative-bias temperature stress, the negative threshold-voltage Vt shift (extracted from the dc current-voltage characteristic) of the direct-tunneling gate p-MOSFET is found to be substantially larger than that calculated based on the interface-state density measured using the charge-pumping method. Device-recovery characteristics from bipolar gate stress show that interface states alone cannot entirely account for the Vt shift, and indicate that a substantial number of positive oxide charges are also generated during stress. Stability of the increased Vt shift under a negative dc gate biasing and unipolar ac gate pulsing implies that these positive charges are deep-level hole traps with energy states above the Si conduction band edge. Because the defect states are outside the energy window of direct electron tunneling, their long relaxation time plays an important role in the slow recovery transient of the p-MOSFET 相似文献