Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

A fast wafer level reliability structure and evaluation method has been developed for stress induced leakage current (SILC) in non-volatile memory processes. The structure is based on parallel floating gate cell arrays. The evaluation method is straightforward, and not time-consuming. The measurement consists of bi-directional FN tunneling stress (to degrade the tunnel oxide and to develop the SILC) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell V_t in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded Flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.     

Stress induced defects and transistor leakage for shallow trenchisolated SOI

Anomalous leakage currents are observed for shallow trench isolated SOI transistors. The leakage effect is caused by stress induced dislocations in the device silicon islands. These dislocations are observed using cross-sectional TEM analysis. For the shallow trench isolation process employed, the leakage is most pronounced on SIMOX wafers when the buried oxide thickness is scaled down to 100 nm. Limiting fabrication stresses to a minimum is critical for eliminating this leakage defect and in obtaining a robust, high yielding SOI STI process     

Temperature dependence of gate induced drain leakage current insilicon CMOS devices

The temperature dependence of the gate induced drain leakage (GIDL) current in CMOS devices is investigated from 20K up to 300K. It is shown that, at sufficiently high electric field, the conventional band-to-band tunnelling GIDL current law is applicable down to near-liquid helium temperatures for both nand p-channel devices. The exponential factor B of the GIDL current law is found to be nearly independent of temperature. Moreover, the decrease of the GIDL current as the temperature is lowered, is shown to originate from the temperature variation of the pre-exponential coefficient A of the GIDL current law     

A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress     

Statistical analysis of subthreshold leakage current for VLSI circuits

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.     

Failure analysis of leakage current in plastic encapsulated packages

Plastic encapsulated packages exhibit high leakage currents after a few hundred hours in the steam pressure pot test (SPP). The present study investigates two possible causes of leakage current. These are: (a) mold compound, (b) the polyimide tape used for co-planarity of lead frame fingers. The results of this study indicate that the leakage cur-rent is independent of the frame and is not caused by the mold compound. The data indicates that it is the ionic content and acrylic-based adhesive layer of the polyimide tape which cause the leakage current. To eliminate the leakage current, polyimide tape with low ionic content and non acrylic-based adhesive should be used. *Permanent address: School of Physics, Universiti Sains Ma-laysia, 11800 USM Penang, Malaysia.     

On stress induced leakage current in 5 and 3 nm thick oxides

The stress induced leakage current (SILC) in Si/SiO₂ structures with thin gate oxides has a steady-state component which increases drastically when the oxide thickness decreases. It is generally agreed that the SILC is due to electron tunnelling trough stress-induced traps. However, it was observed that the SILC, created by Fowler–Nordheim injection, decays continuously when, after stress, the samples are positively or negatively biased at a low voltage. The decay is irreversible as long as the gate oxide is not biased at a high voltage. The present article adds complementary observations. It shows, first that the above phenomenon is observed in 3.5 nm thick oxides, secondly, that this phenomenon is stable as long as the temperature stays below 200°C, and thirdly, that during the SILC decay, the interface state density does not diminish.     

Hot hole stress induced leakage current (SILC) transient in tunneloxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-Å oxide obeys a power law time dependence f^-n with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed     

Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.     

钽电解电容器生产工艺和漏电流分析

钽电解电容器在电子元器件中占据着非常重要的地位,钽电容器是电容器中体积小而又能达到较大电容量的产品,最早在1956年由美国贝尔实验室首先研制成功的,它的性能稳定,可靠性优异,在将尽一个世纪以来没有哪种电容器通过完全替代钽电解电容器,钽电容器封装形式多种多样,体积尺寸设计多样化,其所具备的稳定性高、容量大、小型方便、高性能以及较强的自愈能力等优势使钽电容器不仅广泛在军事通讯,航空航天等领域应用,而且还在向工业控制,影视设备、通讯仪表、手机、电脑、飞机、工业控制电子线路或者火箭雷达等领域扩展,覆盖范围非常广,其地位和重要性在电子电路中可圈可点。文章主要针对钽电解电容器关键生产工艺流程以及漏电流情况做了简单阐述,希望能进一步提高钽电解电容器的生产制造水平。     

氧化锌避雷器泄露电流测量与分析

作为市场中避雷器的一种,氧化锌避雷器在其同类设备中应用效果较好,当各类电子元器件受到损害时,氧化锌避雷器能够较好地对其产生保护作用。另一方面,当发生电流泄露时,操作人员需要及时地将其检测出来,并采取相应的办法对数据进行专业处理和分析。基于此,本文中笔者对氧化锌避雷器泄露电流测量试验分析,并提出相关的防泄漏策略。     

Enhanced gate induced drain leakage current in HfO2 MOSFETs

The substrate current of high-κ dielectric MOSFETs has been studied using dc sweep and transient (down to 100 μs per I-V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO₂/SiO₂ interface and transition layer, and not the result of oxide charging.     

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.     

Low leakage current GaAs diodes

Diodes were formed by Mg ion implantation into n-epitaxial GaAs layers on n⁺Substrates. Deep level transient spectroscopy (DLTS) measurements gave trap densities around 10¹²cm^-3in the epilayers. The reverse-biased junction currents were in the low-to-mid 10^-9A/cm²range at 10-V bias and the diodes had breakdown voltages as high as 250 V.     

Theoretical and experimental analysis of leakage current in InGaAsPBH lasers with p-n-p-n current blocking layers

The dependence of the leakage current in 1.3-μm InGaAsP buried heterostructure (BH) lasers with p-n-p-n current blocking layers on well number, mesa width, and carrier density has been analyzed using a two-dimensional device simulator and compared with the electroluminescence (EL) emitted from InP layers. The analysis of the minority carrier flow reveals that the electron current flowing through the p-n-p-n current blocking layers is the dominant component of the leakage current. The measured EL intensity has two peaks at both sides of the n-blocking layer apart from the active layer. The EL intensity decreases with increasing well number and carrier density of the p-blocking layer, and increases with increasing mesa width. These results are consistent with the simulations     

Model and analysis of gate leakage current in ultrathin nitridedoxide MOSFETs

An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects     

Measurement and analysis of substrate leakage current of RF mems capacitive switches

This paper focused on a new direction of study on leakage current called substrate charge injection. The substrate leakage current of capacitive RF micro-electro-mechanical-system (MEMS) switches was measured, and the conduction mechanism was estimated. The study of the leakage current conduction mechanisms of the substrate dielectric film shows that leakage is mainly induced by hopping conduction at low electric fields, whereas both Schottky emission and hopping conduction may contribute to the leakage current at high fields. The quantitative relationship between the substrate leakage current and the dielectric layer leakage current was also determined for the first time. In the case of low drive voltage (0–30 V), the substrate leakage current significantly contributes to the total leakage current. Results show that the charging properties of the substrate should not be neglected at low drive voltage because such properties could significantly affect the functionality and reliability of RF MEMS switches.     

SJ/T 11383-2008《泄漏电流测试仪通用规范》概要

“泄漏电流”这一术语已经用于表达若干不同的概念,如接触电流、保护导体电流、绝缘特性等。目前设备标准仍然普遍使用该术语表示人体接触电气设备时流过人体的电流,但实际所指的是接触电流。为符合行业的使用习惯,本规范沿用“泄漏电流”术语。     

Scaling effects on gate leakage current

Scaling effects on direct tunneling gate leakage current are analyzed by utilizing new models implemented to perform self-consistent calculation between the direct tunneling, the band-gap narrowing (BGN) and the incomplete impurity ionization. This calculation is indispensable for reproducing the measured gate current-gate voltage characteristics in the device simulation. As a result, it is concluded that the scaling of the gate width cannot suppress the gate leak, even if the specification of the threshold voltage is relaxed in order to shrink the gate width. It is also found that the scaling of the gate length cannot suppress the gate leak unless the vertical field is strong.     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.