Symbolic analysis methods and applications for analog circuits: atutorial overview

This tutorial paper gives an overview of the history and present state of the art in symbolic analysis of electronic circuits at the so-called circuit level. Symbolic analysis is defined as a technique generating a closed-form analytic expression for a circuit characteristic with the circuit's elements represented by symbols. Such analytic information complements the results from numerical simulations. The paper then describes the different application areas of symbolic analysis for the design of analog circuits. Symbolic analysis is mainly used as a means to obtain insight into a circuit's behavior, to generate analytic models for automated circuit sizing, and in applications requiring the repetitive evaluation of circuit characteristics. Next, the present capabilities and limitations of symbolic analysis, both in functionality and efficiency, are discussed. The major symbolic analysis methods are presented, and algorithmic details are provided for symbolic approximation, hierarchical decomposition, and symbolic distortion analysis. Finally, existing symbolic simulators are compared, and directions for future research are pointed out     

Synthesis of Native Mode Self-Test Programs

Recent studies show that at-speed functional tests are better for finding realistic defects than tests executed at lower speeds. This advantage has led to growing interest in design for at-speed tests. In addition, time-to-market requirements dictate development of tests early in the design process. In this paper, we present a new methodology for synthesis of at-speed self-test programs for microprocessors. Based on information about the instruction set, this high-level test generation methodology can generate instruction sequences that exercise all the functional capabilities of complex processors. Modern processors have large memory modules, register files and powerful ALUs with comprehensive operations, which can be used to generate and control built-in tests and to evaluate the response of the tests. Our method exploits the functional units to compress and check the test response at chip internal speeds. No hardware test pattern generators or signature analyzers are needed, and the method reduces area overhead and performance impact as compared to current BIST techniques. A novel test instruction insertion technique is introduced to activate the control/status inputs and internal modules related to them. The new methodology has been applied to an example processor much more complex than any benchmark circuit used in academia today. The results show that our approach is very effective in achieving high fault coverage and automation in at-speed self-test generation for microprocessor-like circuits.     

一种新型混合模式BIST的低功耗设计

本文提出了一种基于折叠集的test-Der-clock结构的混合模式BIST设计方案,并且进行了低功耗的整体优化设计.该设计方案在电路结构上利用双模式LFSR将两部分测试生成器有机的进行了结合,针对伪随机测试序列与折叠测试序列两部分采用了不同的措施来优化测试生成器的设计,从而达到降低被测电路功耗的目的.     

CLA加法器混合式BIST方案

本文以先行进行加法器为例,将确定性测试方法与伪随机测试方法相结合,提出了实现内建自测试电路中测试生成器的、在测试昨测试电路硬件开锁之间取得折衷的几种方案。最后,比较并分析了所得结果。     

A hierarchical approach to large circuit symbolic simulation

This paper presents a new approach to symbolic analysis of large circuits. The proposed procedure is grounded on circuit decomposition by node tearing, symbolic analysis at subcircuit level and circuit function generation. Symbolic analysis is based on matrix-determinant method implemented within our original symbolic simulator. The crucial part of this procedure is circuit function generation. Opposed to classic symbolic simulation that gives final result in canonical sum-of-product form, hierarchical approach results in compact nested form. Proposed method is described in details using a simple example. The comparison with two other similar techniques is given using a benchmark example. The overall time reduction in comparison with the circuit function extraction in fully expanded form is 30 times.     

On methods to match a test pattern generator to acircuit-under-test

Autonomous circuits such as linear feedback shift registers (LFSRs) and cellular automats are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns. Methods to tailor an LFSR to a circuit-under-test are proposed, that attempt to select the most effective LFSR and initial state for the circuit. The first method is based on a learning process that can be applied directly to certain types of circuits. The learning process is also used to establish a collection of (primitive and nonprimitive) LFSRs and initial states, effective for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving the selected LFSR and initial state. The use of an LFSR that can apply complemented as well as uncomplemented test patterns is shown to significantly improve the fault coverage, at the cost of a small area overhead. Experimental results demonstrate the applicability of the proposed approaches to stuck-at faults and to transition faults     

电路测试神经网络方法中求多个测试矢量

文章研究在数字电路测试的神经网络方法中求给定故障对应的多个测试矢量的方法,首先提出了一种求多个测试矢量的遗传进化方法,然后提出了一种矢量扰动方法,通过这两种者的结合使用,能获得被测电路较小的完备测订,从而提高了电路测试神经网络的方法的性能。     

Automated simplified analysis of analogue circuit behaviour based on fully symbolic relations between parameters

Symbolic circuit analysis provides the key for understanding the mechanisms underneath circuit operation, and it can be used to obtain predictive models of circuit behaviour. Symbolic analysis has many applications in the design of analogue circuits but is severely limited by the size of the resulting expressions. Thus an efficient approximation strategy is required for successful symbolic analysis of large analogue circuits. A fully symbolic procedure for the simplification of large expressions, which mimics the heuristic procedures followed by an experienced designer (based on the relations between the parameters of the circuit), is presented in this paper. This simplification strategy is particularly well suited to be combined with some circuit level partition algorithms, leading to a blend between simplification after generation (SAG) and simplification during generation (SDG). The algorithms have been implemented and integrated on a prototype software package for the automated analysis and design of analogue circuits.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

基于遗传算法的数字电路测试生成方法

本文提出了一种基于遗传算法的数字电路测试图形生成方法，首先把被测电路的门级描述转化为易于计算的非线性网络，然后用遗传算法找到网络能量函数的最优解，从而得到被测电路的测试集．这种方法对可测故障都能生成测试，能方便地产生多故障的测试图形，同时具有较好的并行性，易于在多处理机上实现．     

Evolutionary graph generation system with symbolic verification for arithmetic circuit design

A novel graph-based evolutionary optimisation technique for arithmetic circuit synthesis is proposed. Symbolic verification of the generated circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within /spl sim/2.2 h.     

Realizations of parallel and multibit-parallel shift registergenerators

We consider how to realize parallel shift register generators (PSRG) and multibit PSRGs, which can be directly used for parallel frame synchronous scrambling (FSS) in the bit- and multibit-interleaved multiplexing environments. We first describe the structure of PSRGs in terms of three parameters-the state transition matrix, the initial state vector, and the generating vectors. Then we discuss how to determine the three parameters of PSRGs that generate the desired parallel sequences in general. We further develop a method for the realization of minimum length PSRGs, and for the realization of PSRGs with minimized circuit complexity. Finally, we consider how to realize minimal PSRGs for use in multibit-parallel scrambling. The results are summarized in four sets of theorems, and are demonstrated through four examples     

Current-mode square wave generators based on a single CDTA

This paper proposes two designs for current-mode square wave generators based on a current-differencing transconductance amplifier (CDTA). Both the proposed circuits are compact and employ a single CDTA with only two external passive components. The first circuit has a fixed duty-cycle topology and can generate a symmetrical square wave with variable frequency. The second circuit has a variable duty-cycle design and can operate in a current-controlled dual duty-cycle mode with a single-circuit topology. The proposed generators allow independent control of the operating frequency, output amplitude, and duty cycle by tuning diverse circuit parameters. This paper discusses several previous designs for square wave generators and presents the circuit principles, related governing formulas, and nonideal problems for the proposed circuits. In addition, computer simulations and experimental results, which are consistent with those of the theoretical analyses and confirm the feasibility of the new generators, are presented.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

On Design Validation Using Verification Technology

Despite great advances in the area of Formal Verification during the last ten years, simulation is currently the primary means for performing design verification. The definition of an accurate and pragmatic measure for the coverage achieved by a suite of simulation vectors and the related problem of coverage directed automatic test generation are of great importance. In this paper we introduce a new set of metrics, called the Event Sequence Coverage Metrics (ESCMs). Our approach is based on a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. During simulation we monitor, in addition to state and transition coverage, whether certain control event sequences take place or not. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG and behavioral test generation techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph, or exercise an uninstantiated control event sequence.     

A novel method for fault diagnosis of analog circuits based on WP and GPNN

A novel method for fault diagnosis of analog circuits with tolerance based on wavelet packet (WP) decomposition and probabilistic neural networks using genetic algorithm (GPNN) is proposed in this paper. The fault feature vectors are extracted after feasible domains on the basis of WP decomposition of responses of a circuit being solved. Then by fusing various uncertain factors into probabilistic operations, GPNN methods to diagnose faults are proposed whose parameters and structure obtained form genetic optimisations resulting in best detection of faults. Finally, simulations indicated that GPNN classifiers are correct 7% more than BPNN of the test data associated with our sample circuits.     

A Robust Random Number Generator Based on a Differential Current-Mode Chaos

This paper demonstrates a differential current-mode chaos-based circuit used to generate random number sequences, which was implemented on 90-nm CMOS-SOI technology. The proposed design is more suitable for circuit implementation of a chaotic map, and diminishes non-idealities such as asymmetry, offset and low slope values. The differential design also exhibits superior robustness to supply voltage, temperature, and process variations. Behavioral and SPICE simulations are used to show the advantages of the differential chaos circuit in comparison to a single ended version. Furthermore, to validate that the circuit can serve as a white noise generator, a statistical random number generator test, as suggested by the Federal Information Processing Standard (FIPS), was conducted on the simulation results and verified on the hardware. The results of the test demonstrated that the circuit functions with very high robustness.      

Two-stage fuzzy inference system for symbolic simplification of analog circuits

This paper presents a knowledge-based fuzzy approach to symbolic circuit simplification in an effort to imitate human reasoning and knowledge of circuit designer experts. The fuzzy approach differs from the conventional simplification techniques in that it can efficiently combine different input variables to obtain optimal simplified expressions. Additionally, this method was chosen due to its adjustability and interpretability, as well as its ability to manage very complex symbolic expressions. The proposed algorithm uses fuzzy logic to simplify the symbolic circuit transfer functions in two stages. In the first stage, a fuzzy system is applied to directly eliminate nonessential circuit components, resulting simplified circuit topology which also yields simpler transfer function. In the second stage, another fuzzy system is used to further simplify the symbolic transfer function from the already simplified circuit, such that deeper insight into the circuit behavior can be obtained. Symbolic and numerical results show that the fuzzy approach outperforms the conventional techniques in terms of accuracy, expression complexity, and CPU running time.     

A rated-clock test method for path delay faults

Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths     

Sequential circuit test generation using dynamic justification equivalence

Automatic test pattern generation (ATPG) for sequential circuits involves making decisions in the search decision spaces bounded by a sequential circuit. The flip-flops in the sequential circuit determine the circuit state search decision space. The inputs of the circuit define the combinational search decision space. Much work on sequential circuit ATPG acceleration focused on how to make ATPG search decisions. We propose a new technique to improve sequential circuit ATPG efficiency by focusing on not repeating previous searches. This new method is orthogonal to existing deterministic sequential circuit ATPG algorithms.A common search operation in sequential circuit ATPG is justification, which is to find an input assignment to justify a desired output assignment of a component. We have observed that implications in a circuit resulting from prior justification decisions form an unique justification decomposition. Since the connectivity of a circuit does not change during ATPG, test generation for different target faults may share identical justification decision sequences represented by identical decision spaces. Because justification decomposition represents the collective effects of prior justification decisions, it is used to identify previously-explored justification decisions. Preliminary results on the ISCAS 1989 circuits show that our test generator (SEST) using justification decompositions, on average, runs 2.4 and 4.5 times faster than Gentest and Hitec, respectively. We describe the details of justification equivalence and its application in ATPG accompanied with step-by-step examples.