SPP并行I／O处理机的设计与实现

可扩展并行处理机系统有两个需要解决的问题：（１）多级互连网络的延迟；（２）吞吐能力；本文根据ＳＰＰ体系结构的特点和实际应用的需要提出了解决这两个瓶颈问题的有效方法在前端服务器与共享存储器之间设计专用的并行Ｉ／Ｏ处理机作为系统Ｉ／Ｏ设备与ＳＭ／ＳＳＭ的直接数据通路。     

并行ACOS PX7800增强型系统的开发

并行ＡＣＯＳＰＸ７８００增强型系统是作为并行ＡＣＯＳ系列最高档机型开发的新一代超大规模并行计算机。该系统采用最新的ＣＭＯＳ工艺和高度并行化技术，使系统的ＣＰＵ单体性能达到ＰＸ７８００原机种的１．５倍，与此同时，它还在通用计算机领域内首次实现了由３２台处理机构成的共享存储器型并行系统，从而大大提高了基于传统双极技术的超大型通用计算机的性能。     

C＊数据并行语言

Ｃ＊语言是通过对ＡＮＳＩＣ语言进行语法和语义的扩展得到的支持ＳＩＭＤ模式的数据并行语言。它允许用户基于一个ＳＩＭＤ虚拟机描述数据在各个虚处理机上的分布以及对这些数据的并行计算操作，提供了一种简单，有效并与任何特定的机器无关的数据并行编程模型。     

并行文件系统PFS的设计与分析

并行计算机高速处理能力与低速Ｉ／Ｏ设备之间的矛盾目前已成为并行计算机系统中的主要问题之一，因此必须研制高性能的并行文件系统．。本文介绍的ＰＦＳ是为“八六三计划”中“曙光二号”并行计算机设计的并行文件系统，该ＰＦＳ分散Ｉ／Ｏ设备的管理到多个处理结点，使文件能交叉地分布在不同Ｉ／Ｏ结点所控制的物理设备上，以实现最大程度的并行访问。本文阐述了ＰＦＳ的基本设计、实现方法及其性能的粗略分析。     

C^＊数据并行语言及其应用

Ｃ＊语言是通过对ＡＮＳＩＣ语言进行进行语法和语义的扩展得的支持ＳＩＭＤ模式的数据并行语言。它允许用户基于一个ＳＩＭＤ虚机描述数据在各个虚处理机上的分布以及对这些数据的并行计算操作，提供了一处简单，有效并与任何特定的机器无关的数据并行编程模型。介绍了Ｃ＊语言在超级计算机领域中的应用和Ｃ＊并行扩成分，并给出了典型的编程实例。     

基于PDM框架的并行集成技术研究

本文具体论述了基于ＰＤＭ的产品集成开发体系结构及系统集成框架。依据并行工程的产品开发哲理及细化设计循环的思想,分析了ＣＡＤ／ＤＦＭ／ＣＡＰＰ／ＣＡＭ并行集成的实现方法。通过ＯＤＢＣ标准接口的方式实现了与ＭＩＳ、ＭＲＰⅡ系统的集成,有效地达到了企业内部信息资源的共享。基于ＰＤＭ框架来实现ＣＡＤ／ＣＡＰＰ／ＣＡＭ的并行集成是一种较为理想的模式。     

JAPS中通信支撑策略的比较

在分布式并行计算系统中,任务运行时支撑平台的功能和效率对并行执行的效果有着重要的影响,Ｊａｖａ言中的线程机制和ＲＭＩ机制为ＮＯＷ环境下的分布并行应用提供了高效的支持＾「１」。在基于Ｊａｖａ的自动并行编译系统ＪＡＰＳ＾「２」中,设计和实现了分别基于Ｊａｖａ ＲＭＩ和Ｓｏｃｋｅｔ通信支持策略的并行任务支撑平台ＰＴＳＰ;并比较了这两种通信策略对在ＮＯＷ环境下的分布式并行计算的支持能力和系统效率。     

基于PDM框架的并行集成技术研究

本文具体论述了基于ＰＤＭ的产品集成开发体系结构及系统集成框架。依据并行工程的产品开发哲理及细化设计循环的思想,分析了ＣＡＤ／ＤＦＭ／ＣＡＰＰ／ＣＡＭ怕实现方法。通过ＯＤＢＣ标准接口的方式实现了与ＭＩＳ、ＭＲＰＩＩ系统的集成,有效地达到了企业内部信息资源的共享。基于ＰＤＭ框架来实现ＣＡＤ／ＣＡＰＰ／ＣＡＭ的并行集成是一种较为理想的模式。     

高性能并行I／O实现技术分析

本文就实现高性能并行Ｉ／Ｏ的技术问题作了一番比较,认为具有独立Ｉ／Ｏ网的外部并行Ｉ／Ｏ结构是最适于实现高性能并行Ｉ／Ｏ的平台。因而,只有从应用算法研究着手,获取适合并行Ｉ／Ｏ的数据布局类型,并在语言、编译和ＯＳ的支持下实现这种布局和并行Ｉ／Ｏ访问,才有可能达到较理想的性能指标。     

Pentium系统采用SSRAM／SDRAM存储器的性能分析

ＳＤＲＡＭ，ＳＳＲＡＭ对于平衡存储器和ＣＰＵ的带宽，实现主存的猝发访问，提高系统性能价格比有重要意义，本文基于Ｐｅｎｔｉｕｍ处理器，讨论了高速缓存和主存采用ＳＳＲＡＭ，ＳＤＲＡＭ的不同系统实现方法及相对性能，不同的系统实现就是在性能，价格和设计复杂性之间的取舍，此分析同样适用于任何嵌入式一级高速缓存的处
处理器。     

众核处理器中硬件支持的I/O虚拟化优化技术研究

众核处理器中I/O资源被多个处理器核所共享。I/O虚拟化实现了I/O资源的高效共享和安全隔离,被越来越多的处理器设计所采用。硬件支持的I/O虚拟化从体系结构设计时就考虑对I/O虚拟化的支持,提供了一个全面、高效的I/O虚拟化的解决方案。深入研究了硬件支持I/O虚拟化的两大关键技术——DMA重映射技术和中断重定向技术,提出了基于Hint的IOTSB Cache管理方法和基于失效队列的失效方法来对DMA重映射进行优化,提出了多层可操控的中断模型和灵活可控的中断重定向实现方法来对I/O中断重定向进行优化。测试结果表明,提出的硬件支持的I/O虚拟化优化方法以很低的I/O性能开销实现了I/O资源的高效共享,提供了几乎接近无虚拟化环境下的I/O性能。     

异构多核处理器体系结构设计研究

多核技术成为当今处理器发展的重要方向,异构多核处理器由于可将不同类型的计算任务分配到不同类型的处理器核上并行处理,从而为不同需求的应用提供更加灵活、高效的处理机制而成为当今研究的热点.本文从体系结构的角度探讨了异构多核处理器设计中的关键点,从内核结构、互连方式、存储系统、操作系统支持、测试与验证、动态电压调节等方面分析...     

Performance Evaluation of a Parallel Pipeline Computational Model for Space-Time Adaptive Processing

This paper presents further results on the design and implementation of various optimizations based on our earlier work of developing a parallel pipelined model for the computational intensive applications that have multiple processing tasks. Performance evaluation of this model was done by using a real-time airborne radar application that employs a Space-Time Adaptive Processing (STAP) algorithm. This paper focuses on the following four issues: (1) The tradeoffs between increasing the throughput and reducing the latency are examined in more detail when allocating processors among different processing tasks. (2) A multi-threaded design is incorporated into the pipeline model and implemented on a massively parallel computer with symmetric multi-processor nodes, which shows enhanced performance. (3) The disk I/O is incorporated into the parallel pipeline to study its effect on performance in which two I/O task designs have been implemented: embedding I/O in the pipeline or having a separate I/O task. By using a double buffering approach together with the asynchronous I/O, the overall pipeline performance scales well as the number of processors increases. (4) From the comparison of the two I/O implementations, it is discovered that the latency may be improved when merging multiple tasks into a single task. The effect of reorganizing the task structure of the pipeline is discussed in detail. All the performance results shown in this work demonstrate the linear scalability the parallel pipeline model can achieve using a production radar application. Although this paper focuses on the implementation of the parallel pipeline model and uses the results from a STAP application to support the claims of the discovered properties for this pipeline, this model is also applicable to many other types of applications with similar computational characteristics.     

异构多核系统中编译器指导的I/O代理技术

在异构多核系统中,精简设计的从处理器核无法运行操作系统,且不支持终端打印和读写文件等常用I/O操作。为此,提出编译器指导、主处理器代理执行的I/O操作技术,采用信息交互、中断处理等方法,实现聚合代理并优化从处理器代码中的I/O操作功能。实验证明,编译器指导的I/O代理性能比系统级I/O代理高5倍以上。     

KAIST image computing system (KICS): A parallel architecture for real-time multimedia data processing

An efficient parallel architecture is proposed for high-performance multimedia data processing using multiple multimedia video processors (MVP; TMS320C80), which are fully programmable general digital signal processors (DSP). This paper describes several requirements for a multimedia data processing system and the system architecture of an image computing system called the KAIST Image Computing System (KICS). The performance of the KICS is evaluated in terms of its I/O bandwidth and the execution time for some image processing functions. An application of the KICS to the real-time Moving Picture Expert Group 2 (MPEG-2) encoder is introduced. The programmability and the high-speed data-access capability of the KICS are its most important features as a high-performance system for real-time multimedia data processing.     

Integrated performance models for SPMD applications and MIMD architectures

This paper introduces queuing network models for the performance analysis of SPMD applications executed on general-purpose parallel architectures such as MIMD and clusters of workstations. The models are based on the pattern of computation, communication, and I/O operations of typical parallel applications. Analysis of the models leads to the definition of speedup surfaces which capture the relative influence of processors and I/O parallelism and show the effects of different hardware and software components on the performance. Since the parameters of the models correspond to measurable program and hardware characteristics, the models can be used to anticipate the performance behavior of a parallel application as a function of the target architecture (i.e., number of processors, number of disks, I/O topology, etc).     

一种SIMD多DSP数字图像处理系统研究与设计

数字图像处理需要大量的数据运算,要求系统具有很高的数据吞吐量。并行处理结构能较好地满足这一要求。介绍一种SIMD并行多DSP数字图像处理系统。该系统具有避免冲突、能连续处理图像数据、处理器间通信及I/O部分简单、硬件及软件模块化等优点。     

Integrated performance models for SPMD applications and MIMDarchitectures

Introduces queuing network models for the performance analysis of SPMD (single-program, multiple-data) applications executed on general-purpose parallel architectures such as MIMD (multiple-input, multiple data) and clusters of workstations. The models are based on the pattern of computation, communication and I/O operations of typical parallel applications. Analysis of the models leads to the definition of speedup surfaces which capture the relative influence of processors and I/O parallelism and show the effects of different hardware and software components on the performance. Since the parameters of the models correspond to measurable program and hardware characteristics, the models can be used to anticipate the performance behavior of a parallel application as a function of the target architecture (i.e. the number of processors, number of disks, I/O topology, etc.)     

面向高带宽I/O的片上网络优化

在高性能处理器中,I/O带宽需求不断增加,一方面高速接口的通道数目不断增加,另一方面接口传输速率也在逐渐提升.高性能处理器的片上网络必须能够匹配各种高速I/O的带宽需求,且必须保证DM A请求能够正确完成.然而各种高速接口协议与片上网络协议在通信机制上存在较大的差别,可能导致死锁等现象的产生.首先对匹配高性能I/O的片上网络存在的问题进行分析,然后提出一种高带宽I/O设计方法及死锁解决方法.采用解死锁方法的片上网络增强了I/O系统的鲁棒性,同时可以减少片上网络设计及运行时的各种限制,提升I/O性能.最后,将所提出的优化方法应用到高性能服务器处理器芯片中,并进行评测,针对16通道PCIe 4.0接口,双向读写带宽分别达到30 GB/s,在一些特殊场景出现死锁以后,片上网络能自动检测死锁并解除死锁.