Broad-band ATM network architecture based on virtual paths

Broadband transport techniques and network architectures based on the virtual path concept are examined. ATM (asynchronous transfer mode) techniques, when coupled with recent technological innovations, are expected to pave the way for future universal transport networks. The virtual path concept, which exploits the ATM's capabilities, is proposed to construct an efficient and economic network. The concept matches current and anticipated technological trends well. Characteristics and implementation techniques of virtual paths are discussed. Advantages of the virtual path concept and its impact on the transport network architecture are demonstrated. The virtual path strategy is also shown to provide efficiently for networks with dynamic reconfiguration capability which will enhance network performance. Some basic analytical results on the dynamic control effects of virtual paths are provided     

Hardware-software architecture of the SWAN Wireless ATM network

The SWAN (Seamless Wireless ATM Network) system provides end-to-end ATM connectivity to mobile end-points equipped with RF transceivers for wireless access. Users carrying laptops and multimedia terminals can seamlessly access multimedia data over a backbone wired network while roaming among room-sized cells that are equipped with basestations. The research focus on how to make ATM mobile and wireless distinguishes SWAN from present day mobile-IP based wireless LANs. This paper describes the design and implementation of the ATM-based wireless last-hop, the primary components of which are the air-interface control, the medium access control, and the low-level ATM transport and signalling.The design is made interesting by its interplay with ATM; in particular, by the need to meaningfully extend over the wireless last-hop the service quality guarantees made by the higher level ATM layers. The implementation, on the other hand, is an example of hardware-software co-design and partitioning. A key component of the wireless hop implementation is a custom designed reconfigurable wireless adapter card called FAWN (Flexible Adapter for Wireless Networking) which is used at the mobiles as well as at the basestations. The functionality is partitioned three-way amongst dedicated reconfigurable hardware on FAWN, embedded firmware on FAWN, and device driver software on a host processor. Using an off-the-shelf 625 Kbps per channel radio, several of which can be supported by a single FAWN adapter to provide multiple channels, per-channel unidirectional TCP data throughput of 227 Kbps (or, 454 Kbps bidirectional) and per-channel unidirectional native ATM data throughput of 210 Kbps (or, 420 Kbps bidirectional) have been obtained.     

Evolutionary architecture for an all-services ATM access network

This paper presents a flexible concept for a broadband subscriber access network which minimizes investment costs by predominantly using the existing network infrastructure. The target network may consist of either a coaxial tree-and-branch structure or symmetrical copper pairs to the subscriber, and is connected to the central head station with the aid of optical feeder lines which can be implemented or enhanced by a passive optical network (PON). In the event of an increase in bit rate requirements, the coaxial network can be expanded by dividing it into smaller, optically fed subnetworks or by supplementing it with optical overlay systems. Flexibility, expandability and low costs are achieved through the standard ATM format implemented for the signals of all interactive services down to the network termination units on the subscriber side. Those signals are transmitted in the coaxial network in frequency bands above the CATV band in accordance with a multiple of the CATV channel width to ensure that the modulation and demodulation is implemented in a cost-efficient manner while providing ‘bit rate on demand’ for a suitably high number of subscribers. Separation of the network termination unit from the customer premises equipment enables a flexible, cost-efficient subscriber configuration to be selected, existing domestic wiring to be used and several completely different subscriber terminals to be simultaneously connected.     

A novel architecture for queue management in the ATM network

The author presents four architecture designs for queue management in asynchronous transfer mode (ATM) networks and compares their implementation feasibility and hardware complexity. The author introduces the concept of assigning a departure sequence number to every cell in the queue so that the effect of long-burst traffic on other cells is avoided. A novel architecture to implement the queue management is proposed. It applies the concepts of fully distributed and highly parallel processing to schedule the cells' sending or discarding sequence. To support the architecture, a VLSI chip (called Sequencer), which contains about 150 K CMOS transistors, has been designed in a regular structure such that the queue size and the number of priority levels can grow flexibly     

Voice over ATM: an evaluation of network architecture alternatives

This article describes eight application scenarios in which there is a business case for voice over ATM. It then evaluates alternative network architectures for implementing the required network functionality. The article incorporates much of the ongoing work of the ATM Forum and the ITU, but does not restrict itself to standards and implementation agreements. In addition, it evaluates nonstandardized alternatives for ATM transport of voice traffic. There are two main areas: N×64 kb/s structured data transfer, also known as composite cell transport-a network operator may aggregate individual voice calls into N×64 kb/s blocks for transport to an intermediate point in the network. At that point the individual calls need to be remapped into new M×64 kb/s blocks for the next stage of their transport. Architectural alternatives and advantages of remapping are investigated. Interworking of signalling is of two types: network interworking, in which the end users are connected to non-ATM networks and an ATM network is used for backbone transport; and service interworking, in which an ATM user is connected to a non-ATM user. Functionality and architectural alternatives for network and service interworking are evaluated     

一种基于CORBA和TMN结构的ATM网络管理模型

本文给出了一种基于CORBA和TMN结构的ATM网络管理模型。首先介绍模型的OS结构,并将ATM与其传输网SDH进行集成管理;其次定义了该模型在不同域之间交换信息的接口,即所谓的Xcoop。结果表明该模型能够实现分布式网络管理、保证宽带连接业务的端到端QoS,并且有故障管理和配置管理功能。     

Design and architecture of a new space priority mechanism for ATM network nodes

This paper presents the architecture of a new space priority mechanism intended to control cell loss in ATM switches. Our mechanism is a new generic concept called: the multiple pushout. It is based on the utilization of both AAL and ATM features and on a particular definition of the priority bit. Whenever one cell of a message overflows the buffer of an ATM switch, the algorithm causes the switch to discard other cells of the message (including later arrivals). Such discarding frees buffer spaces for cells of other messages that have a chance of arriving at their destination intact. Our objective is to emphasize that in case of overload, with most of proposed mechanisms, cells are discarded without any semantic information about the type of cells. Therefore, at the destination, all the fragments of the corrupted messages will be discarded anyway. Finally, we present simulation results comparing cell loss rates and message loss rates of several space priority mechanisms.     

ATM network resilience

With the prospect of widespread deployment of ATM by public network operators, it is crucial to ensure resilience to network outages caused by cable breaks and node failures. The general aim of resilience is to make network failures transparent to users. If a failure happens to affect a circuit, it would be very desirable to reconfigure that circuit as quickly as possible with no information loss. However, if this functionality incurs a significant cost overhead, it may be necessary to charge customers according to the resilience they receive. Since user requirements vary from service to service, it is highly likely that different customers will demand variable levels of resilience. For example, mission-critical business-oriented data services will rely on virtually fault-transparent service, whereas residential customers may tolerate breaks in service as long as they do not occur frequently or last a long time. Fortunately, different ATM restoration mechanisms are possible which suit varied customer requirements. This article summarizes a range of research papers describing ATM restoration techniques. The viable options to provide ATM network resilience are discussed, along with the customer requirements which they satisfy and aspects of ATM resilience being assessed by standards bodies. Taking all such matters into consideration, conclusions are drawn on the current and future scope for ATM resilience     

ATM test-bed architecture for training purposes

Due to the recent tremendous growth in ATM products, there is a strong need for training and education for engineers working in the field of ATM networks. This paper describes the architecture of an ATM test-bed that can be used to provide such training. Copyright © 2001 John Wiley & Sons, Ltd.     

A scalable ATM switching system architecture

The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers     

Wireless ATM network architectures

Emulated LAN technology supports mobile hosts in wireless ATM networks. This paper introduces virtual LAN (VLAN) services using ATM LAN emulation technology which operates on a client/server model. One of the attractive features of the VLAN is the capability to group users into a broadcast domain. The focus of this paper is the issue of supporting quality of service to mobiles in a wireless ATM network. Copyright © 2001 John Wiley & Sons, Ltd.     

An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

A parallel embedded-processor architecture for ATM reassembly

The asynchronous transfer mode (ATM) reassembly algorithm for adaptation layer five is broken down into concurrent tasks for efficient VLSI implementation. VHDL and HSPICE simulations show that the proposed reassembly chip architecture will function with ATM line rates up to 700 Mb/s. The architecture is based upon three embedded lightweight processors, a variety of supporting circuitry, and a peripheral component interface (PCI) bus host interface. An important architectural feature is the use of a paged memory management system for the reconstruction of variable length messages     

Self-healing virtual path architecture in ATM networks

ATM network techniques have been actively researched and developed with the goal of realizing B-ISDN. ATM networks can transport signals of various services efficiently and economically, and offer the benefit of enhanced flexibility if the virtual path (VP) concept is adopted. Therefore, the ATM network will provide the infrastructure for B-ISDN. One of the most important themes in B-ISDN is the increased level of network reliability required to to match the high volume of data transmission that will be incurred by the information society and the “mission critical” nature of such data. The authors summarize self-healing network (SHN) schemes they have developed, and discuss problems that must be solved to realize SHN     

A novel switching architecture for ATM networks

It is known that the flexibility and capacity of asynchronous transfer mode (ATM) networks can meet the bandwidth requirements of multimedia applications. In ATM networks, switching is one of the major bottlenecks of end-to-end communication. We propose using a multiple partitionable circular bus network (MPCBN) as an ATM switch. Connection requests are first transformed into a graph where vertices and edges represent connection requests and conflicts among connection requests, respectively. We then use a graph traversal algorithm to select a maximal set of requests for execution in physically partitioned buses. An approach of using finite projective planes is then used to reduce the number of switch points from O(N²) to O(N √N), where N is the number of ports of a switch. A performance evaluation for both uniform and bursty data sources shows that the approach of using finite projective planes to reduce the number of switch points results in a small increase of cell loss probability     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Optimum architecture for input queuing ATM switches

An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.<>     

Connection architecture and protocols to support efficient handoffs over an ATM/B-ISDN personal communications network

The next generation personal communication network will likely internetwork wireless networks via the ATM/B-ISDN to enable ubiquitous broadband personal communication services. Support of user terminal mobility, particularly the capability for fast and seamless handoffs, over the ATM/B-ISDN is an expected requirement that is not currently met. We propose extensions to the ATM/B-ISDN user transport and signaling network architectures and signaling protocols to meet these requirements. The new architecture employs the Mobile Virtual Circuit (MVC), a dynamic connection tree in which routes are predetermined but not set up for potential handoff connections. During a handoff, associated signaling using source-routing with a new robust adaptation feature is employed for fast resource allocation to establish the handoff connection by distributed control. We also address the new problem of packet ordering synchronization to enable a seamless handoff. The connection tree reconfigures after each handoff to enable continuous support of successive handoffs. The proposed scheme optimizes handoff delay over the ATM/B-ISDN while minimizing unnecessary resource allocation, chances of handoff failure, and call processing load in the intelligent network, and the extensions are backward compatible to current ATM/B-ISDN standards and implementations.This paper was presented in part in PIMRC'95 in Toronto, and Globecom'95 in Singapore. This work was supported by the Canadian Institute of Telecommunications Research (CITR), funded under the Canadian Federal Government's Networks of Centres of Excellence Program.     

TORUS: terabit-per-second ATM switching system architecture basedon distributed internal speed-up ATM switch

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4×2 switch module using optical interconnection technology and very high-speed crosspoint LSIs, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch