An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.     

A phase-interpolation direct digital synthesizer with an adaptiveintegrator

A phase-interpolation direct digital synthesizer (DDS) with an adaptive integrator is described in this paper. Unlike a conventional DDS, it does not use ROM or a D/A converter. Therefore, less power is dissipated and the maximum speed is increased. The delay time for phase interpolation is generated by the adaptive integrator, which is composed of a capacitance switch array and current switch array, and by a comparator with constant threshold voltage. The DDS was fabricated on 0.5-μm CMOS process technology. The spurious level is lower than -50 dBc and the power dissipation is 60 mW at a clock frequency of 40 MHz and output frequency of about 19 MHz     

A direct digital synthesizer with interpolation circuits

This paper presents a direct digital synthesizer (DDS) with no ROM that still produces square waves with low spurious signals. The main features are the interpolation of the analog-converted accumulator contents and the extraction of timing at the points where the interpolated signal is identical to a continuous sawtooth waveform. Experimental results confirm successful frequency synthesizer operation. The output frequency is determined by the frequency control word, and spurious signals present in the accumulator contents are greatly reduced     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

带高速电流舵DAC的直接数字频率合成器

本文给出了一种高速SiGe BiCMOS直接数字频率合成器设计。该数字频率合成器单片集成了高速DDS数字核,10位差分电流舵 DAC,串/并接口和时钟控制逻辑。芯片采用0.35μm SiGe BiCMOS标准工艺流片,工作在1GHz系统频率。测试结果显示,该DDS能够生成高达400+ MHz的捷变模拟sine波形。     

A direct digital synthesizer with a tunable error feedbackstructure

A basic premise for a direct digital synthesizer (DDS) with error feedback (EF) is that the output frequency being generated is low with respect to the clock frequency used. This is necessary because the transfer function of the EF has zero(s) at DC. In the proposed architecture the clock frequency need only be much greater than the bandwidth of the output signal, whereas the output frequency could be any frequency up to somewhat below the Nyquist frequency. In this novel method, the coefficients of the EF filter are tuned according to the output frequency     

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

This paper describes a 14-b direct digital frequency synthesizer (DDFS) utilizing a sigma-delta noise shaping technique to reduce spurs arising from phase truncation. A new phase accumulator architecture adopting a second-order sigma-delta modulator is proposed. The sigma-delta noise shaping eliminates periodicity inherent in the phase truncation error. With the proposed phase accumulator, the significant spurs are reduced, and the spectral characteristics of the DDFS are then determined by finite precision of sine-amplitude output. A prototype DDFS IC in 0.25-/spl mu/m CMOS was fabricated on 0.12-mm/sup 2/ die area. The measured spurious-free dynamic range (SFDR) is greater than 110 dB for 16-b phase value and 14-b sine-amplitude output. The fabricated IC consumes 100 mW with a 2.5-V supply, and correctly operates up to 250 MHz.     

A low-power segmented nonlinear DAC-based direct digital frequency synthesizer

A 2.5-V CMOS direct digital frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-/spl mu/m CMOS process occupies an active area of 1.4 mm/sup 2/. For a clock frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the clock frequency.     

A low-power direct digital synthesizer using a self-adjustingphase-interpolation technique

A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-μm CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate     

高性能直接数字式低频率合成器设计

针对采用当前方法进行高性能直接数字式低频率合成器设计时,难以计算出直接数字式低频率合成器的查找表地址的宽度,存在输出频率分辨率较低、相位噪声较高的问题,提出一种基于FPGA的高性能直接数字式低频率合成器设计方法。该方法对直接数字式低频率合成器原理进行分析,得到直接数字式低频率合成器的正弦波公式,在此基础上采用进位链与流水线技术相结合的方法计算查找表地址输入的宽度,得到满足查找表内的数据长度范围,并结合相位累加器对数字式锯齿波进行输出,获取数字式锯齿波的若干相位作为ROM的地址输入,然后对输入地址进行查表以及运算处理,由此完成高性能直接数字式低频率合成器设计。实验结果表明所提方法能够有效提高直接数字式低频率合成器的频率分辨率,同时具有较强的抵抗相噪能力。     

A direct digital frequency synthesizer based on ROM free algorithm

An ROM free quadrature direct digital frequency synthesizer (DDFS) was proposed in this paper. The proposed DDFS mainly consists of two adders and two multipliers to generate quadrature outputs. The proposed DDFS was implemented in both cell-base library and ALTERA Stratix EP1S40F780C5 FPGA board for verification.     

基于FPGA的DDS设计

利用现场可编程门阵列(FPGA)设计并实现直接数字频率合成器(DDS).结合DDS的结构和原理,给出系统设计方法,并推导得到参考频率与输出频率闻的关系.DDS具有高稳定度,高分辨率和高转换速度,同时利用Altera公司FPGA内的Nios软核设置和显示输出频率,方便且集成度高.     

Ultrahigh-speed direct digital synthesizer using InP DHBT technology

Direct digital synthesizers (DDS) offer advantages such as precise beam shaping and forming over conventional RF approaches. This paper discusses novel design and process techniques that enable direct digital synthesis of S-band output frequencies using our current InP double-heterojunction bipolar transistor technology with a cantilevered base layer and undercut collector. The DDS chip operates at the world record clock rate of 9.2 GHz and capable of generating sinewaves up to 4.56 GHz. It also demonstrates state-of-the-art phase noise of -140 dBc at a frequency offset of 1 kHz and a clock frequency of 2.5 GHz. Further design and process improvements will be implemented in future generation circuits that will enable synthesis of Ku-band frequencies.     

Single-chip A/D converter for digital microphones with on-chip preamplifier and time-domain noise isolation

A 1-bit sigma-delta modulator (ΣΔM) with an on-chip preamplifier for digital electret microphones has been implemented. A differential gm-opamp-RC preamplifier eliminates the traditional single-ended JFET interface and is integrated with an on-chip ΣΔM by removing all external components. The proposed time-domain noise isolation technique preserves circuit performance under a single power supply condition. The prototype implemented in a 0.18 μm CMOS technology achieves a 78 dB dynamic range and 62 dB peak signal-to-noiset distortion ratio (both A-weighted) with a current consumption of 450 μmA under a 1.8 V supply.     

多通道高速直接数字频率合成器

本文提出了一款具有32位相位精度,输出12位精度的高性能直接数字频率合成器。该直接数字频率合成器通过多通道采样技术和12位精度的数模转换器,使其同时具有高速和高精度的特性。该芯片采用130nm标准CMOS工艺制造,核心区域面积为0.89mm×0.98mm,在1.2V单电源供电情况下,总功耗约为300mW,室温条件下,最大时钟工作频率为2.0GHz。     

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.     

A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current: 11.5 mA).     

A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-/spl mu/m CMOS

A 300-MHz quadrature direct digital frequency synthesizer/complex mixer (QDDSM) chip is presented. With a 32-bit input frequency control word, the tuning resolution is 0.07 Hz at the operating frequency of 300 MHz. The 12-bit I and Q inputs and 13-bit I and Q outputs offer a spurious-free dynamic range of 90.3 dB. The tuning latency is 13 clock cycles, which corresponds to 43 ns at 300 MHz. The tuning bandwidth (half the operating frequency) is 150 MHz. The IC is realized in 0.25-/spl mu/m TSMC CMOS technology with 4180 standard library cells and occupies a core area of 0.36 mm/sup 2/. At 300 MHz, the power dissipation is less than 400 mW. A key feature of the design is the creation of conditionally negating multipliers.     

基于直接数字频率合成器的新型微波成像系统

研究并实现了一种Ku频段的相控阵被动微波成像系统.该系统使用直接数字频率合成器(Direct Digital Synthesizer,DDS)进行上变频后作为射频通道的本振信号,通过DDS作为等效移相单元来实现相控阵成像系统的移相.对比传统使用数字移相器方案,该成像方案可以对视场内的景物进行几乎连续的高密度电扫描,具有扫描时间短、移相精度高、扫描像素高等优点.系统的实测成像结果表明:基于DDS的相控阵微波成像方案具有成像质量高、成像速度快、系统成本较低等优势,是一种有着良好研究前景的新型微波与毫米波成像技术.     

基于直接数字频率合成技术的FM/PM的实现

直接数字频率合成（DDS）是一种可以实现多种调制的新的频率合成技术。调频和调相统称为角度调制。调频是根据调制波的幅度去改变载波的频率;调相是根据调制波的幅度去改变载波的相位。本文在数字电路中实现了模拟调制,大大提高了可移植性和可控性。文章首先介绍了用DDS实现FM、PM调制的基本原理,然后在通用的基带调制硬件平台基础上,给出了一种基于DSP和FPGA实现FM、PM调制的具体方法。最终通过DAC电路,在输出端口得到最终的输出,并且在频谱仪上得到了设定的满足设计要求的所频谱。