Laser‐fired contact optimization in c‐Si solar cells

In this work we study the optimization of laser‐fired contact (LFC) processing parameters, namely laser power and number of pulses, based on the electrical resistance measurement of an aluminum single LFC point. LFC process has been made through four passivation layers that are typically used in c‐Si and mc‐Si solar cell fabrication: thermally grown silicon oxide (SiO₂), deposited phosphorus‐doped amorphous silicon carbide (a‐SiC_x/H(n)), aluminum oxide (Al₂O₃) and silicon nitride (SiN_x/H) films. Values for the LFC resistance normalized by the laser spot area in the range of 0.65–3 mΩ cm² have been obtained. Copyright © 2011 John Wiley & Sons, Ltd.     

Effects of Laminate Architecture on Fracture Resistance of Sponge Biosilica: Lessons from Nature

Hexactinellid sponges are known for their ability to synthesize unusually long and highly flexible fibrous spicules, which serve as the building blocks of their skeletal systems. The spicules consist of a central core of monolithic hydrated silica, surrounded by alternating layers of hydrated silica and proteinaceous material. The principal objective of the present study is to ascertain the role of the latter laminate architecture in the material's resistance to both crack initiation and subsequent crack growth. This has been accomplished through indentation testing on the giant anchor spicule of Monorhaphis chuni, both in the laminated region and in the monolithic core, along with a theoretical analysis of deformation and cracking at indents. The latter suggests that the threshold load for crack initiation is proportional to K_c⁴/E²H where K_c is fracture toughness, E is Young's modulus, and H is hardness. Two key experimental results emerge. First, the load required to form well‐defined radial cracks from a sharp indent in the laminated region is two orders of magnitude greater than that for the monolithic material. Secondly, its fracture toughness is about 2.5 times that of the monolith, whereas the modulus and hardness are about 20% lower. Combining the latter property values with the theoretical analysis, the predicted increase in the threshold load is a factor of about 80, broadly consistent with the experimental measurements.     

Electrical characteristics of thin Ni2Si,NiSi, and NiSi2 layers grown on silicon

We have determined the resistivity, carrier concentration, and Hall mobility as a function of thickness (700–3000 Å) of Ni₂Si, NiSi, and NiSi₂ layers formed by vacuum annealing at 270÷v300°C, ≈ 400°C, and ≈ 800°C, respectively, of nickel films vacuum-deposited on a silicon substrate (111 n-type and 100 p-type Si ρ ≈ 1KΩ). The layer thicknesses were measured by 2 MeV⁴He⁺ backscattering spectrometry. The silicide phase was confirmed by x-ray measurements. The electrical measurements were carried out using van der Pauw configuration. We found the electrical transport parameters to be independent of the film thickness within the experimental uncertainty. The Hall factors were assumed to be unity. The majority carriers are electrons in NiSi and holes in Ni₂Si and NiSi₂. The resistivity values are 24±2, 14±1, and 34±2 μΩcm, the electron concentrations are 9±3, 10 and 7±1, and ≈ 2 × 10²² cm^?3, and the Hall mobilities are 3±1, ≈ 4.5 and 6, and ≈ 9 cm²/Vs for Ni₂Si, NiSi (〈100〉 and 〈111〉), and NiSi₂, respectively. The systematic error in the measured values caused by currents in the high resistivity substrate is estimated to be less than 6% for the Hall coefficient. The results show that Ni₂Si, NiSi, and NiSi₂ layers formed by a thin film reaction are electrically metallic conductors, a result which concurs with those reported previously (1) for refractory metal silicides. The Hall mobility increases with the Si content in the silicide. The electron concentration is lowest for NiSi₂ leading to the highest resistivity for the epitaxial phase of NiSi₂.     

Supercooling studies and LPE growth of Hg1−xCdxTe from Te-Rich solutions

Hg_1-xCd_xTe liquid phase epitaxial (LPE) layers were grown from well-stirred large (100 g) Te-rich Hg-Cd-Te solutions by the dipping method. Supercooling below the liquidus temperature in Te-rich solutions was studied by differential thermal analysis (DTA) and film growth results. Although supercooling of 20 to more than 100° C was routinely measured in small (2 g) sample melts, supercooling in larger melts (>100 g) was erratic and smaller. Factors affecting the degree of supercooling were identified and a Hg-reflux was found to be a major cause of erratic melt behavior. The LPE reactor was modified to correct the Hg-reflux action and a visual technique was developed for in situ determination of the liquidus temperature. A limited amount of supercooling was found in the melt after reactor modification but it was difficult to maintain for extended durations before spontaneous nucleation occurred. Consequently, programmed cooling rather than isothermal LPE was employed to grow many of the films reported here. Hg_1−xCd_xTe epitaxial layers ofx = 0.2 to 0.25 were grown on (111)B oriented CdTe substrates by cooling the melts only 1–2° C below the previously measured crystallization temperature. The small amount of cooling minimized composition variation with film thickness. Excellent surface morphology was obtained when slow cooling rates of 0.02–0.05° C/ min were used. Cooling rates greater than 0.2° C/min created rough, pitted surface. Precise substrate orientation was important in reducing surface terracing. Composition and thickness uniformities of the epitaxial films were excellent as a result of substrate rotation. Run-to-run reproducibility of film composition was ±0.01 inx. Hall measurements showed carrier concentrations in the range 2–20 × 10¹⁴ cm⁻³ with photoconductive lifetimes of 0.5–3.0 dms forx = 0.20 to 0.25.     

Fabrication and characteristics of MOS-FET's incorporating anodic aluminum oxide in the gate structure

Anodic aluminum oxide films have been grown by means of a simple process which is compatible with the existing planar silicon IC fabrication technology. Device structures have been fabricated and tested in order to demonstrate the usefulness of anodized layers of evaporated aluminum in a multiple layer metallization scheme. Results of anodization of thin aluminum layers on a silicon substrate indicate complete conversion of aluminum into aluminum oxide and in addition, formation of a thin underlying layer of silicon dioxide. For the anodic aluminum oxide a growth rate of 11·5 Å/volt at a current density of 0·5 mA/cm² has been found to produce quite satisfactory quality of insulting layers. Experimental results are presented illustrating the C?V and I?V characteristics of p-channel MOS-FET's with both the partially anodized stacked-gate structure and the over-anodized double-oxide layer gate structure.     

Electrical and photoelectric properties of nanostructures obtained by electroless etching of silicon

The electrical and photoelectric properties of nanostructures with porous silicon layers obtained by electroless etching of silicon have been investigated. It is found that the photoelectric and photovoltaic properties of these structures depend on their morphology and are determined by not only the properties of the modified layer, but also the presence of possible barriers in the layered porous silicon. The ratio of the photoconductivity to the dark conductivity reached 10²−5 × 10². An open-circuit voltage V _oc was detected that amounted to ∼250 mV at an incident light power close to AM-1 (∼100 mW/cm²). In this case, the density of short-circuit current I _sc was about 20 μA/cm².     

13·7%-Efficient Zn(Se,OH)x/Cu(In,Ga)(SSe)2 thin-film solar cell

Cu(In,Ga)Se₂ (CIGS) and related semiconducting compounds have demonstrated their high potential for high-efficiency thin-film solar cells. The highest efficiency for CIGS-based thin-film solar cells has been achieved with CdS buffer layers prepared by a solution growth method known as chemical bath deposition (CBD). With the aim of developing Cd-free chalcopyrite-based thin-film solar cells, Zn(Se,OH)_x buffer layers were deposited by CBD on polycrystalline Cu(In,Ga)(S,Se)₂ (CIGSS). A total-area conversion efficiency of 13·7% was certified by the Frauenhofer Institute for Solar Energy Systems. The CIGSS absorber was fabricated by Siemens Solar Industries (California). For device optimization, the thickness and good surface coverage were controlled by XPS–UPS photoemission spectroscopy. A Zn(Se,OH)_x thickness below 7 nm has been found to be optimum for achieving a homogeneous and compact buffer film on CIGSS, with open-circuit photovoltage V_oc=535 mV, fill factor FF=70·76% and a high short-circuit photocurrent density J_sc=36·1 mA cm⁻². Copyright © 1998 John Wiley & Sons, Ltd.     

High voltage photovoltaic mini‐modules

This work describes the design, simulation, fabrication process, and characterization of high voltage photovoltaic mini‐modules using silicon on insulator (SOI) wafers. The mini‐modules are made of a number of small area photovoltaic cells (<1 mm²) monolithically connected in series. Isolation between cells is performed by means of anisotropic etching of the active layer of the SOI wafer. Measurements using standard sunlight (AM1·5 100 mW/cm²) confirm the viability of this technology to fabricate small area arrays showing open circuit voltages, V _oc, between 620 mV and 660 mV and photocurrent densities up to 22·3 mA/cm² for single cells of 0·225 mm² area and 10 µm active film thickness. Series connection scales up V _oc and the maximum power, P _m, from 625 mV and 21·2 µW, respectively, in a single cell to 103 V and 3·2 mW when 169 cells are connected in series in a 0·42 cm² module total area. Copyright © 2008 John Wiley & Sons, Ltd.     

The properties of Si/Si1-xGex films grown on Si substrates by chemical vapor deposition

A growth parameter study was made to determine the proper of a SiGe superlattice-type configuration grown on Si substrates by chemical vapor deposition (CVD). The study included such variables as growth temperature, layer composition, layer thickness, total film thickness, doping concentrations, and film orientation. Si and SiGe layers were grown using SiH₄ as the Si source and GeH₄ as the Ge source. When intentional doping was desired, diluted diborane for p-type films and phosphine for n-type films were used. The study led to films grown at ∼1000°C with mobilities from ∼20 to 40 percent higher than that of epitaxial Si layers and ∼100 percent higher than that of epitaxial SiGe layers grown on (100) Si in the same deposition system for net carrier concentrations of ∼8x10¹⁵ cm^-3 to ∼2x10¹⁷ cm^-3. Enhanced mobilities were found in multilayer (100)-oriented Si/Si_1-xGe_x films for layer thicknesses ≥400A, for film thicknesses >2μm, and for layers with x = 0.15. No enhanced mobility was found for (111)-oriented films and for B-doped multilayered (100)-orlented films. Supported in part by NASA-Langley Research Center, Hampton, VA, Contract NAS1-16102 (R. Stermer & A. Fripp, Contr. Mon.)     

Growth of epitaxial Si1-xGex layers at 750° C by VLPCVD

Silicon-germanium epitaxial layers have been grown on (100) silicon at 750° C by very low pressure chemical vapor deposition (VLPCVD). Pure SiH₄ and GeH₄ were used as the processing gases. Commensurate films of Si_1-x withx < 0.13 have been deposited up to a critical thickness about 2-4 times larger than the equilibrium value. Interrupted growth, controlled by gas switching, was employed to improve interfacial abruptness. The films have been characterized as a function of SiH₄ and GeH₄ flow rates and germanium content. Growth rate and germanium incorporation as a function of GeH₄:SiH₄ input ratio and total gas flow rate have been studied. We observed that the growth rate of the Si_1-x Ge _x layer decreases as the germanium content in the film or the GeH₄:SiH₄ ratio increases at 750° C using VLPCVD. We also found that, for a given GeH₄:SiH₄ ratio, the germanium incorporated in the solid is independent of the total gas flow rate.     

Non-stationary phase transitions in systems metallization of silicon structures

We study the degradation of aluminum metallization under the thermal impact induced by rectangular current pulses with an amplitude of j < 8 × 10¹⁰ A/m² and a length of τ < 800 μs and experimentally investigate the thermal degradation of a metal film under the action of phase transformations, specifically, metal fusion and contact melting in a metal-semiconductor system during the passage of current pulses with a power above the critical value P_cr. It is demonstrated that the main mechanism of the fusion of a metallization stripe is related to heat release at the interface between the liquid and solid phases under the thermal impact. The velocities of liquid-phase propagation (10–50 m/s) along the metallization stripe have been determined in the experiment as a function of the electric power of the current pulse. The stresses in the silicon surface layers near the nonstationary heat source have been estimated. It is shown that current pulses with an electric power of ～0.7P_cr induce the stresses sufficient for the formation of dislocations. The formation of dislocation half-loops in the silicon surface layers near the thermal impact source upon the passage of current pulses with a specified power has been observed.     

Evaluation of the influence of an embedded porous silicon layer on the bulk lifetime of epitaxial layers and the interface recombination at the epitaxial layer/porous silicon interface

Porous silicon plays an important role in the concept of wafer‐equivalent epitaxial thin‐film solar cells. Although porous silicon is beneficial in terms of long‐wavelength optical confinement and gettering of metals, it could adversely affect the quality of the epitaxial silicon layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the epitaxial layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron‐doped (10¹⁶/cm³) epitaxial layers grown on reorganised porous silicon as well as on pristine mono‐crystalline, Czochralski, p⁺ silicon. Surprisingly, the bulk lifetime of epitaxial layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of layers on top of bare p⁺ substrate (32–50 µs). It is believed that proper surface closure prior to epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the epitaxial layer/porous silicon interface was found to be ~250 times more recombinative than an epitaxial layer/p⁺ substrate interface (S ≅ 10³ cm/s). However, the inclusion of an epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.     

Capacitance-Voltage characteristics of metal-insulator-semiconductor diodes with S passivation and Si interface control layers on GaAs and InP

GaAs and InP surfaces have been prepared by gas-phase and liquid-phase polysulfide passivation techniques followed by the deposition of Si interface control layers (ICLs) by e-beam evaporation. For GaAs surfaces, the performance of an ICL consisting of 1.5 nm Si on top of 0.5 nm of Ge has also been evaluated. Metal-insulator-semiconductor diodes with aluminum top electrodes were fabricated on these surfaces using silicon nitride deposited by a remote plasma-enhanced chemical vapor technique or silicon dioxide deposited by a conventional direct plasma-enhanced chemical vapor deposition technique. The quality of the interfaces was analyzed by capacitance-voltage (C-V) measurements and the interface state densities D_it were deduced from the C-V data using the high-low method. Values as low as 1.5 × 10¹² eV⁻¹cm⁻² were obtained for polysulfide-passivated GaAs surfaces with a Ge-Si or Si ICL, the lowest ever demonstrated using the high-low method for an ex-situ technique not involving GaAs epitaxy. For InP, the Si ICL does not reduce D_it below that of 2 × 10¹² eV⁻¹ cm ⁻² that was obtained for the polysulfide passivated surface. The Si ICL produces an interface that degrades more slowly on exposure to air for both GaAs and InP.     

Hyper frequency modeling of resonated systems based on piezoelectric LiTaO3 thin layers

In this work, we discuss the piezoelectric activity of lithium tantalite (LiTaO₃) thin layers and to more understand this phenomenon we have developed a model for our LiTaO₃ resonators based on mason model and simulated the hyper frequency behavior. Our LiTaO₃ resonators are made from three layers staked on silicon substrates. The aluminum thin film constitutes the external electrode, the platinum forms the internal electrode and the lithium tantalite constitutes the piezoelectric layer. Each element of these layers is represented by an arrangement of impedances. The simulation shows the reflection coefficient, ρ, as a function of the frequency. We observe a resonant frequency that decreases with the increase of the thickness of the piezoelectric LiTaO₃ layers. A slight variation of this resonant frequency is obtained when comparing it with that of the uncharged piezoelectric device, which is due to the different layers loading the system. Over oscillations superposing to the envelope are observed and found to be related to the propagation of the acoustic wave in the silicon substrate. From these over oscillations one can see that this system can be used as an efficient method to calculate the thickness of any substrate.     

Anodization of nanoscale Si layers in silicon-on-insulator structures

Anodization of silicon-on-insulator (SOI) layers is studied as a function of the SOI layer thickness in the range from 5 to 500 nm. It is found that thinning of the silicon film to less than 100 nm is accompanied by a sharp decrease in the anodization rate. For SOI films thinner than or on the order of magnitude of ∼10 nm, the limiting thickness of the oxidized silicon layer is 0.4 nm. It is shown that the main cause of a decrease in the anode current efficiency during oxidation of nanoscale Si layers is an increase in the resistance of the silicon active layer, which limits the hole current in the film plane and, hence, the number of silicon cations coming to the SiO₂/electrolyte interface for their subsequent oxidation.     

Microstructure developments and anti-reflection properties of SiO2 films by liquid-phase deposition

In this work, silicon dioxide (SiO₂) films were deposited on a multi-crystalline silicon substrate via liquid-phase deposition (LPD) using hydrofluorosilicic acid (H₂SiF₆) and boric acid (H₃BO₃) aqueous solution. We controlled the surface morphology and grain structure of the film by using the concentration of H₂SiF₆, and the particle sizes were controlled by the concentration of H₃BO₃. Fourier transform infrared spectroscopy showed that three SiO_x peaks exist at 1103, 815, and 463 cm⁻¹, respectively. X-ray diffraction revealed a typical broad peak in the range of 14–55° for the SiO₂ amorphous particles. The refractive index of the LPD film was 1.41. The reflection of the LPD SiO₂ film was affected by the film thickness, and the reflectivity of the film was decreased as the film thickness increased. For the 106 nm SiO₂ film thickness, the average reflectance under the measuring conditions was 14.1%. The low reflectance rendered the film a suitable anti-reflection film in multi-crystalline silicon solar cells.     

Erratum

Epitaxial layers of ZnSe ranging in thickness from 5μm to 30 μm have been grown on GaAs (100) substrates over the temperature range 240° C to 340° C by atmospheric pressure MOVPE employing dimethylzinc and hydrogen selenide. An optimum growth temperature of 280 ± 5° C has been identified and when grown at this temperature the ZnSe epitaxial layers exhibit low resistivity (ρ _{298 K} ≤ 10 ohm · cm), a low compensation ratio (θ _{298 K} = 0.27), a carrier mobility (μ _{298 K} ) of 250 ±10 cm ² V ^-1 s ^-1 ) and are n -type ( n _{298 K} = 8.0 × 10 ¹⁴ cm ^-3 ). The ratio of photoluminescence intensity measured at 298K and at 12 K is high (10 ⁴ ) and is dominated by a sharp emission due to excitons bound to neutral donors at 2.7956 eV. Mass spectrometric investigations of the chemical reactions occurring inside the reactor in the presence of the GaAs substrate indicate significant surface-controlled reactivity in the region of 280° C. The online version of the original article can be found at     

Electrical and photo-luminescence properties of ZnSe epitaxial layers grown on GaAs (100) by atmospheric pressure MOVPE: The role of substrate temperature

Epitaxial layers of ZnSe ranging in thickness from 5μm to 30 μm have been grown on GaAs (100) substrates over the temperature range 240° C to 340° C by atmospheric pressure MOVPE employing dimethylzinc and hydrogen selenide. An optimum growth temperature of 280 ± 5° C has been identified and when grown at this temperature the ZnSe epitaxial layers exhibit low resistivity (ρ_{298 K} ≤ 10 ohm · cm), a low compensation ratio (θ_{298 K} = 0.27), a carrier mobility (μ_{298 K}) of 250 ±10 cm²V^-1s^-1) and aren-type (n _{298 K} = 8.0 × 10¹⁴ cm^-3). The ratio of photoluminescence intensity measured at 298K and at 12 K is high (10⁴) and is dominated by a sharp emission due to excitons bound to neutral donors at 2.7956 eV. Mass spectrometric investigations of the chemical reactions occurring inside the reactor in the presence of the GaAs substrate indicate significant surface-controlled reactivity in the region of 280° C.     

X-ray-emission study of the structure of Si:H layers formed by low-energy hydrogen-ion implantation

Amorphous silicon layers formed by implantation of 24-keV hydrogen ions into SiO₂/Si and Si with doses of 2.7×10¹⁷ and 2.1×10¹⁷ cm^?2, respectively, were studied using ultrasoft X-ray emission spectroscopy with variations in the energy of excitation electrons. It is ascertained that the surface silicon layer with a thickness as large as 150–200 nm is amorphized as a result of implantation. Implantation of hydrogen ions into silicon coated with an oxide layer brings about the formation of a hydrogenated silicon layer, which is highly stable thermally.     

Chemical Vapor Deposition of <Emphasis Type="Italic">α</Emphasis>-Boron Layers on Silicon for Controlled Nanometer-Deep <Emphasis Type="Italic">p</Emphasis><Superscript>+</Superscript><Emphasis Type="Italic">n</Emphasis> Junction Formation

Nanometer-thick amorphous boron (α-B) layers were formed on (100) Si during exposure to diborane (B₂H₆) in a chemical vapor deposition (CVD) system, either at atmospheric or reduced pressures, at temperatures down to 500°C. The dependence of the growth mechanism on processing parameters was investigated by analytical techniques, such as transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), in conjunction with extensive electrical characterization. In particular, devices fabricated by B deposition effectively demonstrated that p ⁺ doping of the silicon substrate can be achieved within 10 nm from the surface in a manner that is finely controlled by the B₂H₆ exposure conditions. High-quality, extremely ultrashallow, p ⁺ n junctions were fabricated, and their saturation current was tuned from high Schottky-like values to low deep pn junction-like values by the increasing of the deposited B layer thickness. This junction formation exhibited high selectivity, isotropy, spatial homogeneity, and compatibility with standard Si device fabrication.